Memory Controller Command Queue Parallel Channel Distribution

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Solution Overview

Problem

Current memory systems face inefficiencies in processing commands due to limitations in distributing commands among multiple channels, leading to suboptimal performance, increased processing time, and wear on memory devices.

Innovation Solution

A memory controller with a command queue and back end channels that generates and distributes optimized back end commands, modifying host commands to combine or eliminate redundant operations, and utilizing a Direct Memory Access module to manage data distribution across channels for improved throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If commands are distributed to multiple back end channels, then productivity is improved, but device complexity increases due to command queue management and distribution logic

Engineering Contradiction:
Improvecommand processing throughputVSAvoidcommand distribution system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The command processing system is segmented into multiple independent back end channels (first back end channel, second back end channel, etc.), each capable of processing commands autonomously. The command queue is divided into multiple channel command queues, with each channel having its own dedicated queue. This segmentation enables parallel command processing across multiple channels, improving throughput while maintaining manageable complexity through modular architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system transitions from single-channel sequential processing to multi-channel parallel processing by adding a channel dimension. Commands are distributed across multiple channels simultaneously, transforming the processing architecture from one-dimensional (single queue, single channel) to two-dimensional (multiple queues, multiple channels), thereby increasing productivity without proportionally increasing overall system complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Loss of time

If host commands are modified to combine or eliminate redundant operations, then loss of time is reduced, but device complexity increases due to command optimization logic

Engineering Contradiction:
Improvecommand processing timeVSAvoidcommand modification logic complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The front end command dispatcher performs preliminary modification of host commands before they are distributed to back end channels. This includes combining multiple commands into single commands and eliminating redundant operations in advance. By performing these optimizations beforehand, the system reduces the total number of commands that need to be processed, thereby reducing overall processing time while confining the complexity to the initial command preparation stage.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The command dispatcher merges multiple host commands into single optimized commands when possible. This combining process consolidates redundant operations and reduces the total command count, leading to faster processing. The merging logic is implemented in the front end dispatcher, which analyzes incoming host commands and combines them before distribution to back end channels.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If data distribution across channels is optimized, then productivity is improved, but device complexity increases due to Direct Memory Access module configuration

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidDMA module configuration complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The Direct Memory Access (DMA) module serves as an intermediary between the command distribution system and the memory devices. It handles data transfer operations independently once commands are distributed to back end channels, eliminating the need for complex coordination between the command dispatcher and memory interfaces. This intermediary approach simplifies the overall system by delegating data management tasks to the DMA module.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10949091B2Memory controllers, memory systems, solid state drives and methods for processing a number of commands
Publication Date: 2021.03.16 MICRON TECHNOLOGY INC
  • US10949091B2 patent drawing
  • US10949091B2 patent drawing
  • US10949091B2 patent drawing

AI summary

The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.