Memory Controller Command Queue Segmentation for Program Fail Recovery
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Solution Overview
Problem
In memory systems with multiple semiconductor memories, existing technologies face challenges in efficiently processing program failures, leading to operational inefficiencies and potential data loss.
Innovation Solution
A memory system with a controller that generates and manages command queues for each semiconductor memory, allowing for queuing and prioritization of commands, and performs program fail recovery operations by holding and re-queuing commands for the failed memory after other memories have completed their operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the controller processes commands for all semiconductor memories simultaneously, then system productivity is improved, but when a program fail occurs in one memory, it causes operational inefficiency and potential data loss in other memories
Solution Approach 1:
The controller divides the command processing into separate command queues for each semiconductor memory. When a program fail occurs in one memory, only the command queue corresponding to that specific memory is affected and held, while other command queues continue processing normally. This segmentation isolates the failure impact to a single memory unit, preventing cascading failures across the entire system.
2Reliability
If the controller holds the command queue for a failed memory, then data integrity is improved, but operational overhead increases due to re-queuing commands after recovery
Solution Approach 1:
The controller maintains command queues in a pre-organized state for each memory, so when a program fail occurs, the commands are already queued and ready to be re-issued once the memory recovers. This preliminary organization of commands minimizes the recovery time and operational overhead, as the controller does not need to re-parse or re-organize commands after detecting the failure.
3Device complexity
If the controller processes commands for multiple memories in parallel, then system complexity is reduced, but difficulty in detecting and measuring program fails increases
Solution Approach 1:
The controller uses separate command queues for each semiconductor memory, which segments the command processing and failure detection. Each command queue is independently monitored for program fails, making it easier to detect and measure failures in specific memories without being obscured by simultaneous operations in other memories. This segmentation maintains relatively simple controller structure while improving failure detection capability.
Data Source
AI summary
There are provided a memory system and an operating method thereof. The memory system includes: a memory device including a plurality of semiconductor memories; and a controller for generating a plurality of command queues respectively corresponding to the plurality of semiconductor memories by queuing a plurality of commands received from a host, and controlling the plurality of semiconductor memories to perform overall operations by outputting the plurality of commands queued in the plurality of command queues, wherein the controller holds a first command queue, among the plurality of command queues, corresponding to a first semiconductor memory, among the plurality of semiconductor memories, in which a program fail has occurred.