Memory Controller Parallel Command Queues for SSD Throughput
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Solution Overview
Problem
All flash array (AFA) servers face delays in read/write operations due to busy times of flash memory chips and increased demand for higher transfer rates with PCIe updates, leading to inefficiencies in accessing SSDs.
Innovation Solution
A memory controller architecture with a flash translation layer, control module, and DMA engine that includes multiple command queues and a codec, allowing parallel execution of commands and retry mechanisms for successful data retrieval from flash memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the AFA server performs a large number of read/write operations on the SSD in a short time, then the transfer rate requirement is met, but the read/write operations are delayed due to the busy time of flash memory chips
Solution Approach 1:
The patent divides the command processing into multiple independent command queues (read command queue, write command queue, retry command queue) and processes commands from different queues in parallel. This segmentation allows the system to handle multiple read/write operations simultaneously, reducing the impact of individual chip busy times and improving overall throughput.
Solution Approach 2:
The patent introduces a time dimension by implementing a retry mechanism with retry command queues. When a read operation fails or returns undecodeable data, the system schedules retry commands in a separate queue, allowing reattempts at different time points when the flash memory chip may be available, thus resolving the time-based conflict.
2Power
If the PCIe version is updated to increase transfer rate demand, then the bandwidth requirement is met, but the number of read/write commands increases significantly causing congestion
Solution Approach 1:
The patent segments the command processing system into multiple independent queues (read, write, retry) that can be processed in parallel. This segmentation prevents command congestion by distributing the increased command load across multiple processing channels, maintaining high transfer rates while managing complexity.
Solution Approach 2:
The patent implements dynamic command scheduling where the arbiter and DMA engine can dynamically select which command queue to process based on current system state, chip availability, and queue depth. This dynamic approach allows the system to adapt to varying command loads from PCIe updates while maintaining efficient throughput.
3Reliability
If the codec fails to decode raw data successfully, then data integrity is compromised, but retrying the read operation increases the busy time of the flash memory chip
Solution Approach 1:
The patent prepares retry commands in advance by maintaining a dedicated retry command queue. When a decode failure occurs, the system can immediately schedule a retry from the pre-prepared queue without needing to re-generate or re-validate the original command, reducing the additional busy time required for retries while maintaining data integrity.
4Productivity
If multiple read/write commands are queued for the same flash memory chip, then command throughput is improved, but command congestion occurs when the chip cannot keep up with the queue
Solution Approach 1:
The patent segments commands destined for the same flash memory chip into different queues based on their operation type (read, write, retry). This segmentation allows the arbiter to manage and space out commands from different queues, preventing congestion while maintaining high throughput by processing ready commands from any queue.
Data Source
AI summary
The present invention provides a memory controller configured to access a plurality of channels, wherein each of the channels includes a plurality flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is configured to generate commands with corresponding physical addresses of at least one of the channels. The plurality of control modules are connected to the plurality of channels, respectively, and each of the control modules operates independently to receive the corresponding command with the corresponding physical address from the flash translation layer, to access the flash memory chips within the corresponding channels.