Memory Controller Dynamic Command Scheduling for NAND Flash
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Solution Overview
Problem
Current memory systems with multiple NAND flash memory chips face performance bottlenecks due to variations in command execution speeds across different memory chips, leading to inefficient access and processing delays.
Innovation Solution
A memory system with a controller that manages multiple queues for each memory chip, dynamically adjusting the order of command transmission based on the processing speed of each chip to optimize parallel execution, ensuring that commands are processed in an order that minimizes delays and maximizes throughput by prioritizing chips with lower execution speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chip interleaving processing is used to access multiple memory chips in parallel, then access performance is improved, but processing delays occur due to variations in command execution speeds across different memory chips
Solution Approach 1:
The patent implements dynamic command transmission ordering that adapts to the actual execution speeds of different memory chips. The controller monitors command execution completion times and adjusts the transmission sequence accordingly, making the system flexible rather than static. This resolves the contradiction by allowing parallel access (improving productivity) while dynamically compensating for speed variations (reducing processing delays).
Solution Approach 2:
The controller incorporates feedback mechanisms by monitoring the execution speeds of individual memory chips and using this information to optimize command transmission ordering. The system continuously gathers performance data from each chip and adjusts its command scheduling strategy accordingly, enabling it to maintain optimal parallel access performance while minimizing delays caused by slower chips.
2Ease of operation
If commands are transmitted to memory chips in a fixed order, then control is simplified, but system efficiency decreases due to inability to account for varying execution speeds
Solution Approach 1:
The system transitions from static fixed-order command transmission to dynamic adaptive ordering. The controller automatically adjusts transmission sequences based on real-time performance monitoring, maintaining ease of operation through automated control while significantly improving system efficiency by optimizing for actual chip speeds.
Solution Approach 2:
The controller performs self-optimization by automatically monitoring execution speeds and adjusting command transmission ordering without external intervention. This self-service capability maintains control simplicity while enabling the system to adaptively maximize its own efficiency based on actual operating conditions.
Data Source
AI summary
According to one embodiment, a memory system includes a nonvolatile memory including a plurality of memory chips and a controller. The controller acquires a first command from a first queue, transmits the acquired first command to a first memory chip, thereafter acquires a second command from a second queue, and transmit the acquired second command to a second memory chip when a first command processing speed based on a time until execution of a command using the first memory chip is completed after transmission of the command to the first memory chip is started is lower than a second command processing speed based on a time until execution of a command using the second memory chip is completed after transmission of the command to the second memory chip is started.