Memory Controller Command Scheduling for Transmission Error Recovery
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Solution Overview
Problem
Data transmission errors between memory controllers and redrive devices lead to increased memory latency and decreased system performance due to the need for corrective actions like replaying commands or retraining links, causing backlogs and delays in processing new commands and data.
Innovation Solution
Implementing a method to detect transmission errors and compare corrective actions between multiple memory controller ports, distributing incoming read commands based on the comparison to minimize delay and optimize availability, and scheduling synchronization commands to prevent data gaps by determining the undesirable half of the core clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If corrective actions are performed in response to transmission errors, then data transmission reliability is improved, but memory latency increases and system performance decreases
Solution Approach 1:
The memory controller dynamically adjusts command scheduling based on the status of corrective actions. When one port is performing corrective actions, the controller dynamically redirects incoming read commands to available ports, adapting the scheduling strategy in real-time to minimize latency while ensuring reliability.
Solution Approach 2:
The patent introduces an intermediary scheduling mechanism that mediates between multiple memory controller ports during corrective actions. This intermediary layer compares the status of corrective actions across ports and intelligently distributes commands, acting as a buffer that prevents direct blocking while maintaining data integrity.
2Reliability
If corrective actions are performed in response to transmission errors, then data transmission reliability is improved, but system productivity decreases due to command backlogs
Solution Approach 1:
The system segments the memory controller into multiple independent ports, each capable of performing corrective actions independently. This segmentation allows the controller to isolate errors to specific ports while other ports continue processing commands, preventing system-wide productivity loss and maintaining overall throughput.
Solution Approach 2:
The patent merges the capabilities of multiple memory controller ports to handle read commands collectively. When one port is occupied with corrective actions, the system combines the resources of other ports to process incoming commands, effectively pooling available capacity to maintain productivity while ensuring reliability.
3Device complexity
If synchronization commands are transmitted without considering clock cycle timing, then device complexity is reduced, but data transmission precision deteriorates due to potential data gaps
Solution Approach 1:
The system performs preliminary analysis of the round-trip time to identify the undesirable half of the core clock cycle before transmitting synchronization commands. This advance planning ensures that commands are scheduled during optimal timing windows, preventing data gaps without requiring complex real-time adjustment mechanisms.
Solution Approach 2:
The patent changes the timing parameter of synchronization command transmission by scheduling them during specific halves of the core clock cycle based on round-trip time analysis. This parameter adjustment optimizes data transmission precision while maintaining relatively simple control logic, avoiding the need for complex dynamic timing adjustments.
Data Source
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AI summary
Systems and methods to respond to schedule commands at a memory controller are disclosed. A transmission error between a first memory controller port and a first redrive device may be detected. A first corrective action may be initiated at the first memory controller port in response to the detection of the transmission error. A particular method may include determining that a second memory controller port initiated a second corrective action. Incoming read commands may be distributed based on a comparison of the first corrective action and the second corrective action.