Memory Controller Command Sequencing for DRAM Time Penalty Reduction
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Solution Overview
Problem
In memory controllers, issuing a Masked Write (MWR) command after a Write (WR) command results in a significant time penalty, leading to performance deterioration due to the longer prescribed interval required between these commands, especially when dealing with burst write operations.
Innovation Solution
A memory controller is designed to issue a first write command for all data in a burst access and a second write command on a per-byte basis, using a holding unit and selection unit to prioritize commands that minimize time penalties by selecting MWR commands when invalid bytes are present or page-misses occur, thereby reducing overall system delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an MWR command is issued to the same bank after a previous WR/MWR command, then data mask control per burst write is enabled, but a long prescribed interval (tCCDMW) of 32 or 64 DRAM clock cycles must be ensured, causing time penalty four times larger than conventional operations
Solution Approach 1:
The patent dynamically selects between MWR and WR commands based on whether invalid bytes are present in the burst write data. The memory controller adapts its command selection in real-time: using MWR when invalid bytes require masking, and using WR when all bytes are valid, thereby optimizing performance based on data characteristics rather than following a fixed command sequence
Solution Approach 2:
The invention changes the command type parameter (MWR vs WR) based on the validity status of bytes in the burst write operation. By detecting invalid bytes and adjusting the command parameter accordingly, the system achieves both data mask control functionality and minimized time penalties, resolving the contradiction between adaptability and time loss
2Manufacturing precision
If MWR command is used for burst write operations with invalid bytes, then data can be selectively overwritten, but the prescribed interval tCCDMW causes deterioration of memory access performance
Solution Approach 1:
The memory controller changes the command parameter dynamically based on data validity information. When invalid bytes are detected, MWR command is selected for precise selective writing; when all bytes are valid, WR command is selected for high-speed writing. This parameter adaptation resolves the contradiction between write precision and access performance
Solution Approach 2:
The system transitions from static command issuance to dynamic command selection based on real-time analysis of burst write data characteristics. The memory controller continuously monitors for invalid bytes and adjusts command type accordingly, achieving both precise data control and optimized performance
Data Source
AI summary
Provided is a controller which issues a first write command for writing all data of a burst access operation on a memory and a second write command for writing data of a burst access operation on a memory per byte. The controller includes a holding unit configured to hold a plurality of commands requesting access to the memory and a selection unit configured to select, in a case where the holding unit holds the second write command and a command that causes a first time penalty longer than a second time penalty needed between the first write command that is issued first and the second write command that is issued next, the second write command prior to the command.