Memory Controller Command Sequencing for Random Read Latency

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Solution Overview

Problem

Current memory systems face challenges in achieving high random read performance and low random read latency due to inefficiencies in command sequencing, particularly in NAND flash devices.

Innovation Solution

A memory controller that dynamically adjusts command sequences based on conditions, sending a first sequence without a read state command when the command queue exceeds thresholds, and a second sequence with read state commands when conditions are met, optimizing performance under varying load scenarios.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a read state command is inserted in the command sequence to ensure proper timing, then reliability of data read is improved, but random read latency increases

Engineering Contradiction:

Improvedata read reliabilityVSAvoidrandom read latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent dynamically adjusts the command sequence based on queue depth conditions. When the command queue depth exceeds a threshold, the system omits the read state command to reduce latency; when queue depth is below the threshold, the read state command is included to ensure reliability. This dynamic adaptation resolves the contradiction by making the timing approach conditional rather than fixed.

Inventive Principle:

Principle #15Dynamics

2Reliability

If commands are processed sequentially with proper waiting periods, then data read reliability is improved, but random read performance deteriorates

Engineering Contradiction:

Improvedata read reliabilityVSAvoidrandom read performance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent segments the command processing into two distinct paths based on queue depth: a fast path that omits the read state command for high-performance scenarios, and a reliable path that includes the read state command for data integrity. This segmentation allows the system to achieve high random read performance when conditions permit while maintaining reliability when needed.

Inventive Principle:

Principle #1Segmentation

3Loss of time

If the command queue threshold is set low, then random read latency is reduced, but data read reliability may be compromised

Engineering Contradiction:

Improverandom read latencyVSAvoiddata read reliability

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The patent changes the operational parameters of the memory controller by introducing a configurable queue depth threshold. This parameter determines when to switch between the fast command sequence (without read state) and the reliable command sequence (with read state). By adjusting this parameter, the system can optimize the balance between latency and reliability based on specific operational requirements.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20260037183A1Memory controllers, memory systems and control methods thereof, memory mediums, and program products

Publication Date: 2026.02.05 YANGTZE MEMORY TECH CO LTD

AI summary

The present disclosure provides memory systems, memory controllers, control methods, computer readable memory mediums, and computer program products. An example method includes: in response to an operation instruction, determining whether a first condition is met; in response to the first condition being met, sending a first command sequence corresponding to the operation instruction to a memory device; and in response to the first condition not being met, sending a second command sequence corresponding to the operation instruction to the memory device.