Memory Controller Compute Expressions for Firmware Algorithm Flexibility
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Solution Overview
Problem
Existing memory controllers face challenges with inflexible and costly hardware-based algorithm execution, as hardware circuits for algorithm execution are fixed and cannot be easily updated or modified, leading to reduced versatility and increased costs due to repeated chip taping and algorithm optimization.
Innovation Solution
A memory controller design that includes a storage device for firmware algorithms and algorithm execution hardware with configurable compute expressions, allowing the processor to dynamically execute firmware algorithms without modifying the hardware, thereby enhancing flexibility and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware circuits are used for algorithm execution, then execution speed is improved, but adaptability deteriorates because hardware circuits are fixed and cannot be easily updated
Solution Approach 1:
The patent implements a dynamic algorithm execution mechanism where the memory controller can load and switch between different algorithm versions stored in memory. The processor dynamically selects and executes algorithms based on configuration information, allowing the system to adapt to different storage device structures and requirements without hardware changes. This resolves the contradiction by making the execution system flexible while maintaining hardware acceleration benefits.
Solution Approach 2:
The patent stores multiple algorithm versions as data in memory rather than hardwiring them into hardware circuits. The processor can load and execute copied algorithm instances from memory, allowing rapid algorithm updates without physical hardware modification. This approach maintains execution speed through hardware acceleration while enabling adaptability through software-based algorithm replacement.
2Productivity
If hardware circuits are modified for algorithm optimization, then execution efficiency is improved, but manufacturing cost increases due to repeated chip taping
Solution Approach 1:
The system uses a dynamic algorithm loading mechanism where optimized algorithms are stored in memory and loaded by the processor as needed. This eliminates the need for repeated chip manufacturing and taping to implement algorithm optimizations. The hardware remains unchanged while execution efficiency is improved through software-based algorithm updates, significantly reducing manufacturing costs.
Solution Approach 2:
Instead of modifying hardware circuits through repeated chip manufacturing, the patent copies optimized algorithm implementations from development environments into the memory system. The processor executes these copied algorithm versions, achieving efficiency improvements without incurring repeated taping and manufacturing costs.
3Ease of manufacture
If fixed hardware circuits are used, then manufacturing cost is reduced, but versatility deteriorates as algorithms cannot be easily updated
Solution Approach 1:
The patent implements a universal algorithm execution architecture where a single hardware platform can execute multiple different algorithms by loading them from memory. The processor and memory system serve multiple functions by dynamically loading different algorithm versions, eliminating the need for separate hardware circuits for each algorithm. This maintains low manufacturing costs while achieving high versatility through software-based algorithm diversity.
Solution Approach 2:
The system copies algorithm implementations into memory for execution rather than hardwiring them into hardware. This allows a single manufactured chip to support multiple algorithms by copying different algorithm versions into memory, maintaining low manufacturing costs while achieving high algorithmic versatility and easy updates.
Data Source
AI summary
The present application discloses a memory controller and operation method thereof, memory system and electronic system. The memory controller includes: a storage device, which is configured to store a firmware algorithm; an algorithm execution hardware, which includes a compute expression, and the compute expression is obtained according to a configuration of the firmware algorithm; and a processor, which is connected to the storage device and the algorithm execution hardware, and the processor is configured to call the algorithm execution hardware to perform the compute expression when executing the firmware algorithm, to obtain a compute result of the firmware algorithm.