Nonvolatile Memory Controller Using Concatenated ECC for High RBER
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Solution Overview
Problem
Current flash storage systems face challenges in meeting target uncorrectable bit error rates (UBER) due to increasing raw bit error rates (RBER) and error floors in error correction codes, particularly with Bose-Chaudhuri-Hocquenghem (BCH) and low-density parity-check (LDPC) codes, which limit their ability to reliably correct data errors.
Innovation Solution
A nonvolatile memory system that employs an outer error correction code concatenated with an inner error correction code, allowing data recovery using either the outer code if its correction capacity is not exceeded, or both codes if exceeded, and optionally utilizing a RAID operation to ensure data integrity, thereby addressing high RBER and error floors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single error correction code (BCH or LDPC) is used, then the device complexity is low, but the reliability is insufficient to meet target UBER due to increasing RBER and error floors
Solution Approach 1:
The error correction function is segmented into two independent codes: an inner code (LDPC) that handles high RBER and an outer code (BCH) that provides additional correction capability. Each code operates independently with its own decoder, dividing the complex problem of correcting high error rates into two manageable stages, thereby achieving target UBER without requiring a single overly complex error correction system
Solution Approach 2:
The patent employs a composite error correction architecture combining two different error correction codes (LDPC and BCH) with complementary characteristics. The inner LDPC code addresses the error floor problem while the outer BCH code provides additional correction capacity, creating a composite system that leverages the strengths of both codes to achieve the target UBER that neither code could achieve alone
2Reliability
If the correction capacity of the outer error correction code is exceeded, then data recovery fails, but implementing multiple error correction codes increases the loss of time due to additional decoding operations
Solution Approach 1:
The inner error correction code (LDPC) is applied first as a preliminary action to correct the majority of errors introduced by high RBER. This preliminary correction reduces the error burden before the outer code (BCH) decoding, increasing the likelihood that the outer code will succeed and reducing the need for time-consuming retry operations or complex fallback mechanisms
Solution Approach 2:
The patent implements a dynamic error correction process where the system adapts to the actual error conditions by attempting inner code correction first, then outer code correction. This dynamic approach allows the system to efficiently handle varying error rates by applying the appropriate level of correction, optimizing the balance between recovery success and decoding time based on the actual data conditions
Data Source
AI summary
A nonvolatile memory controller may recover encoded data using the outer error correction code of the encoded data if it is determined that a correction capacity of the outer error correction code is not exceeded. Alternatively, the nonvolatile memory controller may recover the encoded data using the inner error correction code of the encoded data followed by the outer error correction code of the encoded data if it is determined that the correction capacity of the outer error correction code is exceeded. Additionally, if it is determined that the correction capacity of the outer error correction code is exceed after recovering the data using the inner error correction code, the nonvolatile memory storage module may perform a redundant array of independent disks (RAID) operation to recover the data.