Memory Controller Concurrent Die Programming

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Solution Overview

Problem

Existing semiconductor memory systems face challenges in programming data efficiently, as increasing the number of bits per memory cell leads to longer programming times, and current methods that transfer data twice for different densities on the same die or between dies are inefficient, tying up the data bus and limiting concurrent processing.

Innovation Solution

Implement a memory system that concurrently programs data at a first density per memory cell on one die and a second density per memory cell on another die using a common data transfer, allowing the controller to report successful programming to the host before the second die is complete, enabling faster data availability and efficient storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is transferred twice for different densities (same die or between dies), then storage density is optimized, but data bus efficiency deteriorates and programming time increases

Engineering Contradiction:
Improvestorage densityVSAvoidprogramming time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent combines two separate data transfer operations into a single concurrent transfer operation. The controller simultaneously transfers data to both the first memory die (for first density programming) and the second memory die (for second density programming) over the same data bus, eliminating the need for sequential transfers and reducing total programming time while maintaining optimal storage density

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If data is transferred twice for different densities, then storage efficiency is improved, but data bus availability deteriorates

Engineering Contradiction:
Improvestorage efficiencyVSAvoiddata bus availability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements continuous useful action by keeping the data bus actively transferring data throughout the programming process. Instead of leaving the data bus idle between sequential transfers, the controller maintains continuous data flow by concurrently programming both memory dies simultaneously, maximizing data bus utilization and availability

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If programming is performed sequentially on multiple dies, then programming completeness is ensured, but overall programming speed deteriorates

Engineering Contradiction:
Improveprogramming completenessVSAvoidprogramming speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies preliminary action by preparing both memory dies for concurrent programming before the actual data transfer begins. The controller sets up both dies with appropriate programming parameters and then simultaneously initiates data transfer to both dies, ensuring programming completeness while achieving parallel execution and improved overall programming speed

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10896724B2Non-volatile storage system with reduced program transfers
Publication Date: 2021.01.19 SANDISK TECHNOLOGIES LLC
  • US10896724B2 patent drawing
  • US10896724B2 patent drawing
  • US10896724B2 patent drawing

AI summary

A memory system comprises a plurality of memory dies and a controller (or other control circuit) connected to the memory dies. To reduce the time it takes for the memory system to program data and make that programmed data available for reading by a host (or other entity), as well as persistently store the data in a compact manner that efficiently uses space in the memory system, the data is concurrently programmed as single bit per memory cell (fast programming) and multiple bits per memory cell (compact storage). To accomplish this programming strategy, the controller concurrently transfers data to be programmed to a first memory die and a second memory die. The transferred data is programmed in the first memory die at a single bit per memory cell and in the second memory die at multiple bits per memory cell.