Memory Controller Concurrent Plane Access via Shared Drivers
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Solution Overview
Problem
Existing memory systems, particularly non-volatile NAND flash memories, face limitations in concurrent access to different memory planes due to the need for access line drivers, which restrict simultaneous access during random memory requests.
Innovation Solution
A memory system with a controller and memory architecture that groups memory command and address pairs by plane and page type, allowing concurrent access operations across multiple planes using a common process without individual internal controllers for each plane, by providing shared access line voltages based on page types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory is divided into planes with access line drivers, then memory access operations can be organized by plane and page type, but concurrent access to different planes is limited
Solution Approach 1:
The memory system is segmented into multiple planes, with each plane containing memory cells organized in rows and columns. This segmentation allows the memory to be divided into independent accessable units while maintaining the ability to perform operations on multiple planes concurrently through the controller's management of multiple access line drivers
Solution Approach 2:
The access line drivers are designed to be multi-functional, capable of driving access lines across different memory planes. This universality allows a single access line driver to serve multiple planes, enabling concurrent access operations without requiring dedicated drivers for each plane, thus improving productivity while maintaining ease of manufacture
2Ease of operation
If access line drivers are used for each plane, then memory cells can be accessed systematically, but the ability to concurrently access different planes during random memory requests is restricted
Solution Approach 1:
The controller performs preliminary actions by receiving and buffering multiple memory access requests before execution. Requests are pre-processed and organized by plane and page type, allowing the system to systematically prepare access line driver assignments in advance. This preliminary organization enables faster concurrent execution without sacrificing systematic access control
Solution Approach 2:
The access line driver assignment is made dynamic rather than static. The controller can dynamically assign access line drivers to different planes based on the specific access pattern and timing requirements. This dynamic allocation allows the system to adapt to random memory requests while maintaining systematic access, reducing access time for concurrent operations by optimally utilizing available drivers
Data Source
AI summary
Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. The controller is configured to select a group of memory command and address pairs from the plurality of memory command and address pairs based on the information maintained by the queue. The example apparatus further includes a memory configured to receive the group of memory command and address pairs. The memory is configured to concurrently perform memory access operations associated with the group of memory command and address pairs.