Nonvolatile Memory Controller Concurrent Programming and Threshold Adjustment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current nonvolatile semiconductor memory systems require inefficient data updating processes that involve copying data to RAM, erasing, and re-programming, leading to increased processing time and external command interactions.
Innovation Solution
The integration of a memory controller that concurrently applies program stresses to erased memory cells and adjusts threshold voltages during data copying and programming, reducing the need for external RAM operations and narrowing the threshold voltage distribution among erased cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data updating is performed by copying to external RAM, erasing, and re-programming sequentially, then data integrity is maintained, but data updating time is excessively long
Solution Approach 1:
The patent combines multiple sequential operations (copying data to RAM, erasing block, programming updated data) into a single concurrent operation. The memory controller performs threshold voltage adjustment on erased cells simultaneously with programming operations, merging what were previously separate sequential steps into parallel execution, thereby reducing total updating time while maintaining data integrity through coordinated control of these operations
Solution Approach 2:
The patent applies preliminary threshold voltage adjustment to erased memory cells before the programming operation completes. By adjusting the threshold voltage of erased cells during the programming process rather than after completion, the system prepares the memory state in advance, allowing subsequent operations to proceed faster without compromising data integrity
2Reliability
If multiple sequential operations are performed for data updating, then operation reliability is ensured, but processing complexity increases
Solution Approach 1:
The memory controller is designed with multi-functionality to handle multiple operations simultaneously. It can perform data copying, threshold voltage adjustment, and programming operations through a unified control architecture, reducing the need for separate dedicated circuits for each operation while maintaining operational reliability through integrated control logic
3Ease of manufacture
If threshold voltage distribution is not narrowed after erasing, then programming simplicity is maintained, but memory cell reliability deteriorates
Solution Approach 1:
The patent performs threshold voltage adjustment as a preliminary action immediately after erasing memory cells and before programming. By narrowing the threshold voltage distribution of erased cells in advance, the system ensures better programming reliability and reduced variability in programmed states, while the automation of this process through the memory controller maintains operational simplicity
4Reliability
If data copying to external RAM is performed, then data backup is achieved, but external processing time increases
Solution Approach 1:
The patent merges the data copying operation with the threshold voltage adjustment and programming operations into a single concurrent process. The memory controller coordinates these operations so that data is copied to RAM while threshold voltage adjustments are being applied and programming is occurring, eliminating the need for separate sequential execution of these steps and reducing external processing time while maintaining data backup reliability
Data Source
AI summary
Integrated circuit memory devices utilize techniques to improve the timing of data update operations within a non-volatile memory, by more efficiently combining memory cell programming operations with threshold voltage adjust operations on erased memory cells. These adjust operations operate to narrow a threshold voltage distribution between memory cells that remain in an erased state after the programming operation has been performed. An integrated circuit memory device may include at least a first block of non-volatile memory cells and a volatile memory device, which has a data storage capacity equivalent to at least a capacity of the at least a first block of non-volatile memory cells. A memory controller is also provided, which is electrically coupled to the at least a first block of non-volatile memory cells and the volatile memory device. The memory controller is configured to, among other things, control data update operations within a block of data stored within the first block of non-volatile memory cells.


