Memory Controller Concurrent Testing for Semiconductor Reliability
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Solution Overview
Problem
The existing methods for pre-shipment inspection of semiconductor memories with true random number generators are inefficient due to the inability to conduct concurrent reliability tests on multiple devices, leading to increased testing time and cost, as true random numbers are unpredictable and device-specific.
Innovation Solution
A memory device with a memory controller that performs separate reliability tests on the memory array and random number generator using distinct test commands, allowing for concurrent testing by using a fixed random number value for the memory array and self-testing the random number generator for irreproducibility, thereby reducing the processing load and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If concurrent reliability testing is performed on multiple semiconductor memories with true random number generators using common test patterns, then testing cost and time are reduced, but the test cannot be performed because true random numbers are device-specific and unpredictable
Solution Approach 1:
The reliability test is segmented into two separate phases: first testing the memory array using a common test pattern, then testing the random number generator using its generated values. This segmentation allows the memory array to be tested concurrently across multiple devices while the RNG is tested individually, resolving the contradiction between concurrent testing efficiency and device-specific randomness requirements
Solution Approach 2:
The memory array is tested first with a common test pattern before the random number generator test is performed. This preliminary action on the memory array using standardized patterns enables concurrent testing across multiple devices, while the subsequent RNG test handles the device-specific randomness requirement
2Reliability
If separate reliability tests are performed on memory array and random number generator, then testing accuracy is improved, but testing time and complexity increase
Solution Approach 1:
The two separate test sequences (memory array test and RNG test) are merged into a single integrated reliability test flow that can be initiated by a single test command. The memory controller coordinates both tests, allowing them to be performed in sequence within one testing session, thus maintaining high testing accuracy while reducing overall testing time compared to completely separate test procedures
Data Source
AI summary
A memory controller performs a reliability test only on a memory array out of the memory array and a random number generator on receipt of a memory test command from a testing device while performing a reliability test only on the random number generator out of the memory array and the random number generator on receipt of a random number test command from the testing device.