Memory Controller Concurrent Write and Garbage Collection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current memory devices face challenges in reducing write latency due to limitations in managing memory blocks and performing garbage collection efficiently, leading to deteriorated write performance.

Innovation Solution

A memory controller with a buffer memory and processor that stores data from a host and the memory device, selects victim memory blocks for garbage collection, reads valid data, updates it, and writes it to a target block, thereby reducing write latency by performing garbage collection concurrently with write operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If garbage collection is performed sequentially after write operations, then memory block management is simplified, but write latency increases

Engineering Contradiction:
Improvewrite latencyVSAvoidmemory block management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent merges garbage collection operations with write operations by using the same target memory block for both purposes. When write data and valid data from garbage collection are destined for the same block, the system combines these operations into a single programming action, thereby reducing write latency while managing complexity through unified operation handling.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system performs preliminary actions by identifying and preparing target memory blocks for both write operations and garbage collection in advance. By pre-selecting victim blocks for garbage collection and comparing them with intended write targets, the system can optimize operation sequencing and reduce overall latency without significantly increasing management complexity.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If garbage collection is performed frequently, then memory performance is maintained, but write operations are interrupted

Engineering Contradiction:
Improvewrite throughputVSAvoidwrite operation continuity
Core Design Contradiction:
ProductivityVSDuration of action of moving object

Solution Approach 1:

The patent combines garbage collection and write operations into a single unified operation by directing both valid data from garbage collection and new write data to the same target memory block. This merging allows the system to perform garbage collection frequently without interrupting write operations, as both operations are executed simultaneously in the same destination block, thereby maintaining both high throughput and operational continuity.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If write operations and garbage collection are performed separately, then operation management is simpler, but overall system efficiency decreases

Engineering Contradiction:
Improvesystem efficiencyVSAvoidoperation management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system merges separate write operations and garbage collection into a single combined operation by identifying when both operations target the same memory block. When overlap is detected, the system executes a unified programming operation that handles both new write data and valid data from garbage collection simultaneously, improving system efficiency while managing complexity through centralized control logic.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system performs preliminary analysis by comparing the target block of incoming write operations with victim blocks selected for garbage collection. This preliminary comparison enables the system to identify opportunities for operation merging in advance, allowing efficient combined execution without significantly increasing real-time management complexity during actual write and garbage collection operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11029854B2Memory controller for concurrently writing host data and garbage collected data and operating method thereof
Publication Date: 2021.06.08 SK HYNIX INC
  • US11029854B2 patent drawing
  • US11029854B2 patent drawing
  • US11029854B2 patent drawing

AI summary

In a memory controller for controlling an operation of a memory device, the memory controller includes a buffer memory and a processor. The buffer memory stores first data received from a host and second data received from the memory device. The processor controls the memory controller to generate a write command for programming the first data and the second data to the memory device.