Memory Controller Error Propagation for Corruption Tracking
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Solution Overview
Problem
Existing memory systems, particularly in non-server contexts like mobile devices, face challenges in tracking and logging memory errors efficiently, as they often lack server-grade reliability features due to power consumption and circuit area considerations, making it difficult to maintain data integrity.
Innovation Solution
Implementing a memory controller that forces uncorrectable errors for corrupted data, tracks both correctable and uncorrectable errors, and uses demand scrub circuitry to correct errors on-chip, while maintaining a poison indicator to propagate error status without requiring additional memory fields, thus improving memory reliability with minimal power and area impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If server-grade memory reliability features (redundant storage, extensive ECC fields) are implemented, then memory reliability is improved, but power consumption and circuit area increase significantly
Solution Approach 1:
The patent extracts only the essential error tracking and logging functionality from comprehensive server-grade memory reliability systems. It implements a streamlined error tracking mechanism that monitors memory errors and logs them without requiring full redundant storage or extensive ECC fields, thereby achieving acceptable memory reliability while significantly reducing power consumption and circuit area overhead.
2Reliability
If server-grade memory reliability features (redundant storage, extensive ECC fields) are implemented, then memory reliability is improved, but circuit area increases
Solution Approach 1:
The patent extracts only the essential error tracking and logging functionality from comprehensive server-grade memory reliability systems. It implements a streamlined error tracking mechanism that monitors memory errors and logs them without requiring full redundant storage or extensive ECC fields, thereby achieving acceptable memory reliability while significantly reducing power consumption and circuit area overhead.
3Reliability
If corruption indicators are tracked for all data blocks, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory system into distinct components: memory controller circuitry that manages error tracking, memory circuitry that stores data and corruption indicators, and logging circuitry that records errors. This segmentation allows corruption indicators to be tracked for data blocks in a structured manner, improving data integrity while managing device complexity through organized modular architecture.
Solution Approach 2:
The patent introduces a memory controller as an intermediary between the memory system and external agents. The memory controller circuitry maintains corruption indicators, arbitrates access requests, and manages error logging, thereby simplifying the overall system complexity by centralizing control functions rather than distributing complexity across all components.
4Reliability
If memory errors are tracked and logged extensively, then memory reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic error logging rather than continuous monitoring. The memory controller circuitry tracks corruption indicators and logs errors at specific intervals or when certain conditions are met, rather than continuously processing and logging all memory operations. This periodic action reduces power consumption while still maintaining adequate memory reliability through systematic error tracking.
Data Source
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AI summary
Techniques are disclosed relating to improving memory reliability, e.g., in the context of memory circuits with limited reliability features. In some embodiments, memory controller circuitry is configured to communicate with memory circuitry via an interface that supports link error detection. The memory controller circuitry may, based on a corruption indicator, transmit a data and parity combination for the first data block that causes the memory circuitry to detect an uncorrectable write interface error. Subsequent reads of the location may therefore cause an uncorrectable error indication. This may advantageously allow the memory controller circuitry to propagate a corruption indicator as an uncorrectable error in the memory circuit, without requiring additional tracking of the indicator by the memory circuit or memory controller, in some embodiments.