Memory Controller CRC Aggregation for DMA Data Integrity
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Solution Overview
Problem
Existing data integrity methods in storage systems face challenges due to software and hardware issues, particularly in Direct Memory Access (DMA) technology, where data corruption can occur during data transfer, and Cyclic Redundancy Check (CRC) implementation consumes processing resources and has vulnerabilities.
Innovation Solution
A computing system that segments and recombines data blocks with incorporated CRC values, calculates logic block CRCs, and combines them to verify data integrity through a memory controller and storage device, minimizing redundant CRC calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Cyclic Redundancy Check (CRC) is used to verify data integrity, then data corruption detection capability is improved, but processing resources are consumed significantly
Solution Approach 1:
The patent segments data into multiple data blocks, each with its own CRC value, and further divides them into logic blocks. This segmentation allows CRC verification to be performed on individual blocks rather than entire data sets, reducing the processing burden while maintaining comprehensive integrity verification across all data
Solution Approach 2:
The patent performs CRC verification selectively on logic blocks rather than all data blocks, and uses combined CRC values for efficiency. This partial action approach verifies critical data paths while avoiding redundant verification of already-protected data segments, optimizing the balance between reliability and resource consumption
2Productivity
If DMA technology is used for data transfer, then data transfer efficiency is improved, but data corruption risk increases due to bypassing processor operations
Solution Approach 1:
The patent calculates and attaches CRC values to data blocks before DMA transfer occurs. By preparing verification data in advance, the system enables post-transfer integrity verification without requiring processor involvement during the actual data transfer, thus maintaining both high transfer efficiency and data integrity
Solution Approach 2:
The patent implements a feedback mechanism where CRC values are calculated for transferred data blocks and compared against expected values. This feedback loop detects corruption that may have occurred during DMA transfer, allowing the system to identify and handle corrupted data while maintaining the efficiency benefits of DMA operations
3Reliability
If data is segmented and recombined into logic blocks, then data integrity verification is improved, but device complexity increases
Solution Approach 1:
The patent designs the memory controller to perform multiple functions: data block segmentation, CRC value attachment, logic block recombination, and CRC verification. By consolidating these functions into a single controller component, the patent manages complexity while achieving comprehensive data integrity verification across the storage system
Data Source
AI summary
A computing system for verifying data integrity is provided, including a host device comprising a memory controller, and a storage device. The memory controller receives original data blocks, each having an associated initial CRC value. The memory controller then segments and recombines the data blocks into logic blocks. The storage device is configured to write the logic blocks to its non-volatile memory of the storage device in the write operation, calculate a new logic block (LB) CRC value for each logic block, and calculate a combined LB CRC value. After the write operation, the memory controller combines duplicated copies of a given CRC value for each of the original data blocks, then combines them together to calculate a combined segments CRC value, and compares the combined segments CRC value to the combined LB CRC value. When the combined CRC values match, a verification response is generated verifying data integrity.