Memory Controller CRC Verification for DMA Data Integrity

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing data integrity methods in storage systems face challenges due to software and hardware issues, particularly in Direct Memory Access (DMA) technology, where data corruption can occur during data transfer, and Cyclic Redundancy Check (CRC) implementation consumes significant processing resources and has gaps in data paths.

Innovation Solution

A memory controller segments and recombines data blocks into logic blocks, calculates new CRC values for each, writes them to non-volatile memory, and compares combined CRC values to verify write integrity, while minimizing redundant calculations during read and write operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If CRC protection is implemented to verify data integrity, then data reliability is improved, but processing resources are significantly consumed

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing resources
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the data path into distinct sections with CRC checks performed at specific boundaries (e.g., after DMA transfer completion, before storage). This segmentation allows CRC verification to occur only at critical transition points rather than continuously throughout the entire data path, reducing overall processing overhead while maintaining data integrity verification.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs CRC calculations in advance during the write operation before data is actually stored to non-volatile memory. By calculating and storing CRC values preliminarily with the data blocks, the system avoids the need to recalculate CRC during read operations, significantly reducing processing resources consumed during data retrieval while maintaining reliable integrity verification.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If CRC checks are performed continuously throughout the data path, then data integrity is improved, but gaps in protection are eliminated

Engineering Contradiction:
Improvedata integrityVSAvoiddata path complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces CRC values as intermediary elements that mediate between data blocks at different stages of the data path. Instead of implementing continuous complex monitoring mechanisms, the system uses these intermediary CRC checksums attached to data blocks to verify integrity at key transition points, simplifying the overall data path architecture while maintaining comprehensive protection.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If processing hardware is used to calculate CRC values, then data integrity verification is improved, but processing speed is reduced

Engineering Contradiction:
Improvedata integrity verificationVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent performs CRC calculations during the write operation before data is stored to non-volatile memory. By completing these computationally intensive calculations preliminarily when the system has available processing capacity, the patent avoids blocking or slowing down subsequent read operations, thereby maintaining high processing speed for data retrieval while ensuring thorough integrity verification.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4607356A1Device and methods for managing the data integrity of read and write operations
Publication Date: 2025.08.27 LEMON INC(GB)
  • EP4607356A1 patent drawingFigure 1
  • EP4607356A1 patent drawingFigure 2
  • EP4607356A1 patent drawingFigure 3

AI summary

A computing device (10) for verifying data integrity is provided, comprising a memory controller configured to receive (202) a plurality of original data blocks. Each original data block has an associated initial CRC value. The memory controller (14) then segments and recombines (204) the received data blocks into logic blocks, and calculates (206) a new logic block CRC value for each logic block. The logic blocks are transmitted (208) with their respective new logic block CRC values to a storage device, and the logic blocks are written (210) to nonvolatile memory of the storage device in a write operation. After the write operation, a combined CRC value is calculated (212) for the logic blocks and a combined CRC value for the original data blocks, and compare (214) the combined CRC values. The memory controller determines (216) whether the combined CRC values match.