Memory Controller Data Allocation for Write Performance
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Solution Overview
Problem
Existing memory systems face challenges in maintaining storage capacity and data write performance, as the write performance varies depending on the area in the memory device and the migration of data, leading to inefficiencies in data storage and retrieval.
Innovation Solution
A memory system with a memory controller that strategically allocates data between different areas of memory blocks, prioritizing writes to areas with single-level cells for speed and multi-level cells for capacity, and performs garbage collection and data migration based on available free blocks and valid data percentages to maintain performance and capacity references.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written to first area with single-level cells for faster write speed, then data write performance is improved, but storage capacity is reduced
Solution Approach 1:
The memory device is divided into multiple areas with different cell types: first area with single-level cells (SLC) for fast writes, second area with multi-level cells (MLC) for high capacity, and third area with triple-level cells (TLC) for maximum capacity. This segmentation allows the system to simultaneously maintain fast write performance in SLC area while preserving total storage capacity through MLC and TLC areas.
Solution Approach 2:
Different areas of the memory device are assigned different quality characteristics: the first area uses SLC with superior write speed and endurance, the second area uses MLC with balanced performance, and the third area uses TLC with highest density. This local quality differentiation enables the system to optimize for both speed and capacity in different locations.
2Quantity of substance
If data is migrated from first area to third area to increase storage capacity utilization, then storage capacity is improved, but data write performance deteriorates
Solution Approach 1:
The memory controller performs garbage collection operations in advance to proactively migrate data from first area (SLC) to third area (TLC) before the SLC area becomes full. This preliminary action prevents performance degradation by maintaining sufficient free space in the high-speed SLC area for incoming write operations.
Solution Approach 2:
The memory controller periodically monitors the usage status of different areas and performs periodic garbage collection operations to maintain optimal data distribution. This periodic maintenance ensures that data is systematically migrated from fast but limited SLC area to high-capacity TLC area over time.
3Reliability
If garbage collection is performed frequently to maintain free memory blocks above threshold, then reliability is improved, but system performance deteriorates due to additional operations
Solution Approach 1:
The memory controller continuously monitors the number of free memory blocks and valid data percentages in each area, using this feedback to dynamically adjust garbage collection operations. When free blocks fall below a threshold, garbage collection is triggered to restore reliability, but only when necessary to avoid unnecessary performance overhead.
Solution Approach 2:
The system dynamically changes operational parameters such as garbage collection frequency and data migration thresholds based on current memory usage conditions. This adaptive parameter adjustment allows the system to maintain reliability while minimizing the performance impact of garbage collection operations.
Data Source
AI summary
A memory system, a memory controller and an operating method are disclosed. A first area, a second area included in the first area, and a third area are set. An area to which target data is to be written is determined to the first area or the third area. When the target data is written to the first area, the target data is preferentially written to the second area. The number of data bits stored per memory cell in the first area is less than the number of data bits stored per memory cell in the third area. As a consequence, it is possible to secure storage capacity of the memory system to at least a set reference while securing data write performance of the memory system recognized by a host to at least a set reference.