Memory Controller Data Dispersion for Flash Read Speed

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Solution Overview

Problem

In flash memory systems, writing data into multiple physical pages of the same logical address range slows down data reading speed due to sequential access of the same memory module, leading to decreased performance.

Innovation Solution

A method and memory controller configuration that disperses writing data belonging to the same logical address range across different rewritable non-volatile memory modules, allowing for parallel reading from multiple modules to maintain data reading speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data belonging to the same logical address range is written into multiple physical pages of the same memory module sequentially, then the writing operation can be completed, but the reading speed decreases due to sequential access requirements

Engineering Contradiction:
Improvewriting throughputVSAvoidreading speed
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The patent segments the storage system into multiple independent memory modules (first memory module, second memory module, etc.), each capable of parallel access. By distributing data belonging to the same logical address range across different physical modules, the system enables parallel read operations, thus maintaining high reading speed while completing write operations.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the memory controller accesses the same memory module multiple times for sequential writes, then data integrity is maintained, but access time increases and performance decreases

Engineering Contradiction:
Improvedata integrityVSAvoidaccess time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent combines multiple memory modules into a unified storage system managed by a single memory controller. The controller maintains a mapping between logical addresses and physical locations across modules, allowing it to distribute writes across multiple modules while ensuring data integrity through coordinated management. This merging enables parallel access patterns that reduce total access time.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9235501B2Memory storage device, memory controller thereof, and method for programming data thereof
Publication Date: 2016.01.12 PHISON ELECTRONICS
  • US9235501B2 patent drawing
  • US9235501B2 patent drawing
  • US9235501B2 patent drawing

AI summary

A memory storage device, a memory controller thereof, and a method for programming data thereof are provided. The memory storage device comprises a rewritable non-volatile memory chip having a plurality of rewritable non-volatile memory modules, and each rewritable non-volatile memory module comprises a plurality of physical blocks. The method includes receiving a write command from a host system, and a logical address corresponding to the write command belongs to a predetermined logical address range. The method also includes determining whether a suitable memory module has not stored any data belonging to the predetermined logical address range exists in all rewritable non-volatile memory modules. The method further includes writing a writing data corresponding to the write command into the suitable memory module if it is existent.