Memory Controller Data Distribution Characterization for Power-Off Stability

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Solution Overview

Problem

Existing memory systems face challenges in maintaining data integrity and efficiency over prolonged power-off periods due to voltage and data distribution changes in memory cells, leading to performance deterioration and reduced reliability.

Innovation Solution

A memory system and operating method that involves programming test data and meta-data before a power-off state, allowing for data distribution checks upon power-on, adjusting parameters based on data offsets, and performing operations like garbage collection and wear leveling to maintain system performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If test data and meta-data are programmed before power-off to enable post-power-on data distribution checks, then data processing reliability is improved, but device complexity increases due to additional programming operations and metadata management

Engineering Contradiction:
Improvedata processing reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by programming test data and metadata into memory blocks before power-off occurs. This allows the system to have characterization data ready for post-power-on verification, enabling reliability checks without adding complexity during actual data processing operations. The metadata contains information about voltage distributions and data patterns that can be used to adjust parameters after power-on.

Inventive Principle:
Principle #10Preliminary action

2Stability of the object's composition

If parameter adjustments are made based on data offset checks, then memory cell performance stability is improved, but operation time increases due to additional checking and adjustment steps

Engineering Contradiction:
Improvememory cell performance stabilityVSAvoidoperation time
Core Design Contradiction:
Stability of the object's compositionVSLoss of time

Solution Approach 1:

The patent performs data distribution characterization and metadata generation in advance before power-off, so that when the system powers on, the adjustment process can use pre-analyzed data. This reduces the time penalty during critical operations by shifting the analysis work to beforehand periods when the system has more flexibility.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback by reading back the programmed test data, comparing it with the original test data using metadata, and using the detected data offsets to adjust programming parameters. This closed-loop feedback mechanism ensures memory cell performance stability while allowing for parameter optimization based on actual observed deviations.

Inventive Principle:
Principle #23Feedback

3Reliability

If data distribution changes due to voltage variations are monitored and compensated, then data integrity is improved, but system complexity increases due to additional monitoring and adjustment mechanisms

Engineering Contradiction:
Improvedata integrityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces metadata as an intermediary that stores characterization information about test data distributions, voltage patterns, and memory block properties. This metadata acts as a reference that simplifies the comparison process during data integrity verification, avoiding the need for complex real-time analysis of raw memory states while still enabling thorough integrity checks.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10318200B2Memory system capable of reliably processing data with reduced complexity and performance deterioration, and operating method thereof
Publication Date: 2019.06.11 MIMIRIP LLC
  • US10318200B2 patent drawing
  • US10318200B2 patent drawing
  • US10318200B2 patent drawing

AI summary

A memory system may include: a memory device including a plurality of pages each having a plurality of memory cells coupled to a plurality of word lines and suitable for storing data, and a plurality of memory blocks each having the pages; and a controller suitable for programming test data to a first memory block among the memory blocks before a first time point, and programming meta-data corresponding to the program of the test data to a second memory block among the memory blocks, in case where the memory system including the memory device is changed from a power-on state to a power-off state at the first time point.