Memory Controller Data Placement for Low-Latency System Reads
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Solution Overview
Problem
Existing memory systems with non-volatile memory, such as SSDs and UFS devices, face challenges in improving read latency due to inefficiencies in data management and garbage collection processes, which can result in system data being written to slower memory areas, leading to reduced read performance.
Innovation Solution
A memory system that includes a memory controller capable of distinguishing between system data and user data based on host address ranges, write commands, or usage patterns, and strategically writes system data to faster SLC areas while moving user data to QLC areas during garbage collection, ensuring high-speed read access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is written to QLC areas during garbage collection, then storage capacity is improved, but read latency increases
Solution Approach 1:
The patent segments the non-volatile memory into multiple areas with different characteristics (SLC areas for high-speed access and QLC areas for high-capacity storage). By dividing the memory space and assigning different data types to different segments, the system achieves both high storage capacity and low read latency for critical system data.
Solution Approach 2:
The patent applies local quality by giving different storage areas different properties - SLC areas provide fast read/write performance while QLC areas provide high density. System data is locally optimized for speed in SLC areas, while user data can be stored in higher-capacity QLC areas, allowing each location to serve its specific purpose optimally.
2Ease of operation
If system data and user data are treated equally during garbage collection, then processing simplicity is maintained, but read performance deteriorates
Solution Approach 1:
The patent extracts system data from the general data pool and separates it from user data during garbage collection processing. By identifying and extracting system data (using host address ranges or data identification flags), the system can prioritize its placement in SLC areas, improving read performance while maintaining relatively simple processing through automated identification rules.
Solution Approach 2:
The patent implements feedback mechanisms where the memory controller continuously monitors access patterns and dynamically adjusts data placement decisions. By tracking which data is accessed frequently and where data is currently stored, the system can make intelligent decisions about moving data between SLC and QLC areas, optimizing read performance based on actual usage patterns.
Data Source
AI summary
A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to perform a write operation on the non-volatile memory in response to a write command from a host by writing system data in a first mode to a first block of the non-volatile memory, the first mode being a write mode for writing data with a first number of bits per memory cell, writing user data in the first mode to a second block of the non-volatile memory when the write command is of a first type, and writing user data in a second mode to a third block of the non-volatile memory when the write command is of a second type. The second mode is a write mode for writing data with a second number of bits larger than the first number of bits per memory cell.