Memory Controller Data Recovery After Storage Failure

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Solution Overview

Problem

Modern storage devices face challenges in reducing resource dedication duration during write operations and managing inconsistent states caused by unexpected power losses, especially in high-density non-volatile storage like TLC flash, which increases the risk of data loss and requires re-sending write operations.

Innovation Solution

The memory system sends confirmation of a successful write operation before detecting success from the underlying non-volatile memory, allowing for earlier resource release and data recovery, and in case of power loss, it cancels write operations to one type of non-volatile memory and writes data to another type, ensuring data integrity without disrupting the host system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the memory system waits for confirmation from underlying non-volatile memory before releasing resources, then data integrity is ensured, but resource dedication duration increases

Engineering Contradiction:
Improvedata integrityVSAvoidresource dedication duration
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The memory controller performs preliminary actions by sending confirmation to the host system before actually verifying write success from non-volatile memory. This allows the host to release resources earlier while the controller still has time to detect and handle potential write failures, resolving the contradiction between early resource release and data integrity verification.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If the memory system uses high-density non-volatile storage like TLC flash, then storage capacity increases, but the time and energy required for calibration increases

Engineering Contradiction:
Improvestorage capacityVSAvoidcalibration time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The memory controller implements feedback mechanisms to monitor write operation status and detect power loss conditions. When power loss is detected during calibration or write operations, the controller can interrupt operations, preserve data in volatile buffers, and resume calibration or rewriting after power restoration, significantly reducing the time loss associated with high-density storage calibration.

Inventive Principle:
Principle #23Feedback

3Productivity

If the memory system continues write operations during power loss, then data writing is maintained, but inconsistent states occur upon recovery

Engineering Contradiction:
Improvewrite operation continuityVSAvoiddata consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The memory controller prepares for power loss by maintaining volatile buffers that can preserve write data temporarily. When power loss is detected, the controller can interrupt ongoing write operations to non-volatile memory, preserve data in volatile buffers, and later rewrite the data to non-volatile memory after power restoration, preventing inconsistent states while maintaining write operation continuity.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

4Reliability

If the memory system sends confirmation after detecting success from non-volatile memory, then data integrity is confirmed, but resource release is delayed

Engineering Contradiction:
Improvewrite success confirmationVSAvoidresource release time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The memory controller performs the preliminary action of sending confirmation to the host system before actually detecting success from non-volatile memory writes. This reversal of the conventional sequence allows the host to release resources immediately upon receiving confirmation, while the controller continues to monitor and verify the actual write success, thereby reducing resource release time without compromising data integrity confirmation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10872008B2Data recovery after storage failure in a memory system
Publication Date: 2020.12.22 MICRON TECHNOLOGY INC
  • US10872008B2 patent drawing
  • US10872008B2 patent drawing
  • US10872008B2 patent drawing

AI summary

Exemplary methods, apparatuses, and systems include a memory controller receiving a first physical address corresponding to a logical address and data and initiating storage of the data at the first physical address. The memory controller sends a message indicating that the data has been successfully stored at the first physical address before determining if the data was successfully stored at the first physical address. Upon determining that the data failed to store at the first physical address, the memory controller retrieves the data from a volatile memory associated with the first physical address. The memory controller sends a request and receives a second physical address for the retrieved data. The memory controller initiates storage of the data at the second physical address.