Memory Controller Data Replication for Read Latency
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Solution Overview
Problem
Current memory systems face inefficiencies in data read operations due to varying times required for program, read, and erase operations across different memory chips, which can lead to increased data read times when one memory chip is performing operations for data other than the requested data.
Innovation Solution
A memory system comprising multiple memory chips and a controller with multiple CPUs, where data is programmed and stored as identical data across multiple chips based on importance information, allowing for selective reading from a chip not performing operations for different data, thereby reducing read times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data is stored in a single memory chip, then storage capacity is optimized, but data read time increases when the chip is performing other operations
Solution Approach 1:
The patent applies the copying principle by storing identical data across multiple memory chips. When data is written to the memory system, it is duplicated across several chips, allowing the controller to read from any available chip, thereby reducing read time when one chip is occupied with other operations.
Solution Approach 2:
The patent segments the data storage function across multiple independent memory chips rather than relying on a single chip. This segmentation allows parallel operations where different chips can handle different tasks simultaneously, improving overall system throughput and reducing read delays.
2Productivity
If data is copied across multiple memory chips, then data read speed is improved, but storage space is reduced
Solution Approach 1:
The patent applies local quality by differentiating the treatment of data based on its importance level. High-importance data is copied across multiple chips to ensure fast read access, while low-importance data is stored in fewer chips. This selective replication optimizes read speed for critical data while minimizing the impact on overall storage capacity.
3Productivity
If multiple CPUs are used to control memory chips, then operation parallelism is increased, but controller complexity increases
Solution Approach 1:
The controller is segmented into multiple independent CPUs, each responsible for controlling specific memory chips through dedicated channels. This segmentation enables parallel processing of multiple memory operations simultaneously, improving throughput while distributing the control complexity across separate processing units rather than requiring a single complex controller.
Data Source
AI summary
A memory system includes a plurality of memory chips, including a first memory chip and a second memory chip, and a controller. The controller includes a first central processing unit (CPU) to process a request received from a host, and a plurality of second CPUs to respectively control operations of the plurality of memory chips through a plurality of channels. An importance table is stored in the controller and includes information about a data programming method for data stored in the memory system, the information about the data programming method corresponding to importance information of the data. The second CPUs are configured to program at least some of the data in both the first memory chip and the second memory chip, based on the importance table, so that at least some of the data is stored in both the first memory chip and the second memory chip as same data.