Memory Controller Allocation for Swap and User Data Separation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high cost of host memory, such as DRAM, and the need for additional storage capacity is addressed by utilizing external memory, like SSD, which is designed to complement host memory functions.
Innovation Solution
A memory system with a memory controller that manages first and second memory cells, where first cells store user data and second cells store swap data from host memory, using different types of memory cells (SLC, MLC, TLC, QLC) and controlling write/read operations based on logical to physical address mapping and cycle time thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If host memory capacity is increased to meet growing storage demands, then storage capacity is improved, but cost increases
Solution Approach 1:
The patent combines host memory (DRAM) and external memory (SSD with SLC/MLC/TLC/QLC cells) into a unified memory system managed by a single controller. This merging allows the system to leverage both the high speed of DRAM and the high capacity/cost-effectiveness of SSD, achieving increased storage capacity without proportionally increasing cost.
Solution Approach 2:
The memory controller is designed to universally manage multiple types of memory cells (DRAM, SLC, MLC, TLC, QLC) through a unified interface and control logic. This multi-functionality allows the system to adaptively allocate different memory types for different purposes (e.g., SLC for swap data, QLC for user data), optimizing both capacity and cost.
2Quantity of substance
If external memory is used to supplement host memory, then storage capacity is improved, but system complexity increases
Solution Approach 1:
The external memory is segmented into different types of memory cells (SLC, MLC, TLC, QLC) with distinct functions. SLC cells are designated for storing swap data requiring frequent access, while MLC/TLC/QLC cells store user data. This segmentation allows each memory type to be optimized for its specific purpose, managing complexity through functional separation.
Solution Approach 2:
The memory controller acts as an intermediary between the host and the heterogeneous memory cells. It translates host memory access requests into appropriate operations on different memory cell types, managing the complexity of interfacing with multiple memory technologies through a unified control layer.
3Speed
If swap data is stored in high-end memory cells, then access speed is improved, but cost increases
Solution Approach 1:
Different memory cell types are assigned to different data types based on their specific requirements. SLC cells with superior write endurance and faster access speeds are locally allocated to store swap data, while MLC/TLC/QLC cells are used for user data. This local quality optimization ensures that high performance is provided only where needed, rather than uniformly across all storage.
4Quantity of substance
If memory cells are used beyond their cycle time threshold, then storage capacity utilization is improved, but reliability decreases
Solution Approach 1:
The system proactively monitors the cycle times of memory cells and performs preliminary actions (data migration, wear leveling) before the cells reach their endurance limits. By detecting when cells approach their cycle time thresholds and redistributing data in advance, the system maintains high capacity utilization while preventing reliability degradation from excessive wear.
Data Source
AI summary
In certain aspects, a memory system coupled to a host memory includes a memory device. The memory device includes first memory cells and second memory cells. The memory system further includes a memory controller coupled to a host and the memory device. The memory controller is configured to write at least one of a first data to the first memory cells or a second data to the second memory cells. The first data includes user data, and the second data includes swap data from the host memory.