Memory Controller Error Detection Using Dynamic-Bus-Inversion

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Solution Overview

Problem

Existing error detection methods in communication systems are inadequate in detecting burst errors affecting multiple bits or symbols, leading to high miss-detection probabilities, especially when combined with error-detection codes that focus on single-bit errors.

Innovation Solution

The use of coding constraints associated with encoding techniques, such as Dynamic-Bus-Inversion (DBI), in conjunction with error-detection and correction codes to identify and correct both burst errors and single-bit errors by generating and comparing error-detection information, facilitating probabilistic determination and remedial action.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If error-detection codes focusing on single-bit errors are used, then single-bit error detection capability is improved, but burst error detection capability deteriorates

Engineering Contradiction:
Improvesingle-bit error detection capabilityVSAvoidburst error detection capability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent combines coding constraints (such as DBI encoding rules) with traditional error-detection codes to create a hybrid error detection mechanism. The coding constraints check for violations of encoding rules (indicating burst errors), while the error-detection codes check for single-bit errors, achieving comprehensive error detection capability for both error types simultaneously.

Inventive Principle:
Principle #5Merging (Combining)

2Device complexity

If traditional error detection methods are used, then implementation simplicity is improved, but error detection accuracy deteriorates

Engineering Contradiction:
Improveimplementation simplicityVSAvoiderror detection accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent segments the error detection process into two independent stages: first checking coding constraints (simple rule-based validation), and then checking error-detection codes (mathematical verification). This segmentation maintains implementation simplicity by using straightforward checks while improving error detection accuracy through the combined power of both methods.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9459952B2Code-assisted error-detection technique
Publication Date: 2016.10.04 RAMBUS INC
  • US9459952B2 patent drawing
  • US9459952B2 patent drawing
  • US9459952B2 patent drawing

AI summary

A method of operation in a memory controller is disclosed. The method includes generating first error information for a selectively dynamic-bus-inversion (DBI)-encoded data word. The selectively DBI-encoded data word is for transfer to a memory device. Second error information associated with the selectively DBI-encoded data word is received from the memory device. Errors in the data word are detected by comparing the first error information to the second error information. The detecting includes evaluating the DBI-encoding of the selectively DBI-encoded data word.