Memory Controller DBI Signaling Without a Dedicated Control Pin

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Solution Overview

Problem

Conventional Data Bus Inversion (DBI) techniques in memory systems require an additional control pin, making them burdensome for narrow memory device interfaces, which often leads to DBI encoding being unused in such applications.

Innovation Solution

Utilizing a portion of the code-space provided by an error detection correction (EDC) code to indicate whether read data is DBI-encoded, eliminating the need for a dedicated DBI control pin by incorporating write and read circuitry with EDC encoders and DBI encoders to conditionally invert data bits based on threshold criteria.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a separate control pin is used for DBI control, then DBI encoding can be implemented, but the pin count increases making it burdensome for narrow memory device interfaces

Engineering Contradiction:

ImproveDBI encoding capabilityVSAvoidpin count

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the DBI control function with the existing EDC code-space. Instead of using a separate control pin, the DBI indication is embedded within the EDC code structure that already exists for error detection and correction. This combining of functions eliminates the need for additional pins while maintaining DBI capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The EDC code-space is made multi-functional by using it both for its traditional error detection/correction purpose and for indicating DBI encoding status. This universal usage of existing code-space allows the system to convey multiple types of information through the same channel, avoiding additional pin requirements.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Device complexity

If DBI encoding is not used in narrow memory devices, then pin count is reduced, but power delivery network optimization is lost

Engineering Contradiction:

Improvepin countVSAvoidpower delivery efficiency

Core Design Contradiction:

Device complexityVSLoss of energy

Solution Approach 1:

The patent combines DBI encoding capability with the existing EDC infrastructure in narrow memory devices. By embedding the DBI indication within the EDC code-space rather than requiring a separate control pin, the system can now implement DBI encoding in narrow interfaces where it previously could not be used, thereby optimizing power delivery without increasing pin count.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11683050B2Memory controller and method of data bus inversion using an error detection correction code

Publication Date: 2023.06.20 RAMBUS INC

AI summary

Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.