Memory Controller (De)compression for Bandwidth Bottlenecks
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Solution Overview
Problem
Conventional methods of storing data in compressed format in DRAMs lead to bottlenecks in memory transfer bandwidth due to complex and time-consuming processes for determining addresses, which negatively impact data transfer efficiency and require multiple system bus cycles.
Innovation Solution
Implementing a system that decompresses data at the memory controller, aligns compressed data on default alignment boundaries, and selectively controls the burst-mode protocol to optimize data transfer, reducing memory controller computations and storage penalties while maintaining efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in compressed format in DRAM, then memory space is saved, but memory transfer bandwidth is reduced due to complex address determination processes
Solution Approach 1:
The patent pre-allocates fixed-size storage regions for compressed data blocks, determining their locations before compression occurs. This eliminates the need for complex post-compression address calculations, as the memory controller already knows where each compressed block will be stored, thus maintaining high memory transfer bandwidth while enabling space-efficient compression
Solution Approach 2:
The patent divides memory into multiple fixed-size regions, each capable of holding a compressed data block. By segmenting memory into predetermined slots with known addresses, the system avoids the need for dynamic address allocation and complex bookkeeping, thereby preserving memory transfer efficiency while implementing compression
2Quantity of substance
If conventional compression schemes are used, then space is saved, but multiple system bus cycles are required for each memory access
Solution Approach 1:
The patent performs preliminary allocation of fixed-size memory regions for compressed blocks before compression takes place. This advance preparation eliminates the need for multiple system bus cycles during actual memory access operations, as the memory controller can directly access predetermined locations without iterative address calculation
Solution Approach 2:
The patent changes the fundamental parameter of data block size from variable (conventional compression) to fixed (this invention). This parameter change simplifies the memory access protocol, allowing single bus cycle operations instead of multiple cycles, thereby reducing access time while maintaining compression benefits
3Quantity of substance
If data blocks are stored without pre-allocated locations, then compression efficiency is improved, but address determination becomes time-consuming
Solution Approach 1:
The patent establishes fixed-size storage regions in advance, creating a predetermined addressing scheme that eliminates time-consuming address determination. Compressed blocks are placed into these pre-defined slots, maintaining compression efficiency while enabling O(1) address lookup time
Solution Approach 2:
The patent uses fixed-size memory slots that can be quickly allocated and deallocated. These simple, uniform storage units serve as efficient placeholders for compressed data, allowing rapid address determination through straightforward indexing rather than complex calculation
Data Source
AI summary
Systems, methodologies, media, and other embodiments associated with (de)compressing data at a time and in a location that facilitates increasing memory transfer bandwidth by selectively controlling a burst-mode protocol used to transfer data to and/or from a memory are described. One exemplary system embodiment includes a memory controller configured to (de)compress memory, to manipulate size data associated with compressed data, and to selectively manipulate a burst-mode protocol employed in transferring compressed data to and/or from random access memory.