Memory Controller Defect Database for Clustered Failure Repair
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Solution Overview
Problem
Existing memory array chip repair methods are inefficient due to extensive custom circuit design, reduced operating frequency, and physical constraints, which cannot address all types of defects, especially clustered failures, and consume significant array area with redundant elements that are often unused.
Innovation Solution
A memory controller and method that avoids using defective locations by identifying and marking them as invalid, preventing writes and data retrieval from these locations, allowing for continued operation without row replacement, and utilizing stored defect information to manage memory allocation effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory repair methods using redundant rows and columns are implemented, then defective locations can be repaired, but array area is consumed by redundant elements and operating frequency is reduced
Solution Approach 1:
The patent extracts the repair functionality from the physical array structure by separating defect information into an external defect database. Instead of embedding redundant repair elements within the array, the defect locations are identified and stored separately, allowing the main array to operate at full speed without the overhead of repair circuitry.
Solution Approach 2:
The patent introduces an intermediary defect database that mediates between the physical array and the control logic. This database stores defect information and enables the system to avoid defective locations through software/firmware management rather than requiring hardware repair circuits, thus maintaining operating frequency while achieving repair capability.
2Reliability
If redundant array elements are added for repair purposes, then defect coverage is improved, but array area consumption increases
Solution Approach 1:
The patent extracts repair functionality from the array structure itself and relocates it to an external defect database. This eliminates the need for physical redundant rows and columns within the array, freeing up array area while maintaining the ability to handle defects through logical management of defect information.
Solution Approach 2:
The patent changes the approach from physical redundancy to informational redundancy. Instead of adding physical repair elements, the system uses defect location information stored in a database to logically manage and avoid defective areas, achieving repair capability without increasing physical array area.
3Reliability
If custom repair circuits are implemented, then defective addresses can be detected and routed to spares, but device complexity increases
Solution Approach 1:
The patent replaces the mechanical/custom hardware repair circuitry with a software/firmware-based solution. Instead of implementing complex custom circuits for defect detection and routing, the system uses a defect database and control algorithms to manage defective locations, significantly reducing hardware complexity.
Solution Approach 2:
The patent creates a universal defect management system that can handle various types of defects without requiring specialized repair circuits for each case. The defect database and control logic provide a multi-functional approach that works across different defect scenarios, eliminating the need for extensive custom circuit design.
4Ease of manufacture
If physical proximity constraints are applied to repair elements, then routing is simplified, but adaptability to different defect locations is reduced
Solution Approach 1:
The patent moves the repair capability from the spatial dimension to the informational dimension. Instead of constraining repair elements to be physically close to defects for routing simplicity, the system uses a defect database that can store and manage information about any defect location in the array, providing full adaptability without physical constraints.
Data Source
AI summary
In one embodiment, a controller for an associative memory having n ways contains circuitry for sending a request to search an indexed location in each of the n ways for a tag, wherein the tag and an index that is used to denote the indexed location form a memory address. The controller also contains circuitry, responsive to the request, for sending a set of n validity values, each validity value indicating, for a respective way, whether the indexed location is a valid location or a defective location. Additionally, the controller contains circuitry for receiving a hit signal that indicates whether a match to the tag was found at any of the indexed locations, wherein no hit is ever received for a defective location.