Memory Controller Defective Cell Compensation via Address Translation
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Solution Overview
Problem
As memory devices increase in capacity and shrink in size, the number of defective memory cells, including both failed and weak cells, increases, leading to reduced operational reliability and manufacturing yield, with existing technologies inadequately addressing the need to detect and efficiently repair weak memory cells.
Innovation Solution
A memory system that generates a second address based on a first address indicating a defective memory cell, allowing for sequential transmission of commands to access and write/read data from both the defective and a corresponding boost memory cell sharing the same bit line or sense amplifier, effectively compensating for degraded characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacity of a memory device increases and the dimension shrinks, then the storage capacity increases, but the number of defective memory cells increases
Solution Approach 1:
The patent performs preliminary detection of weak memory cells during manufacturing or initialization, storing their addresses in advance. This allows the system to proactively compensate for defective cells before they cause operational failures, rather than reacting to failures after they occur.
Solution Approach 2:
The patent introduces a memory management unit (MMU) as an intermediary between the host and the memory device. The MMU maintains a mapping table that translates logical addresses to physical addresses, enabling it to redirect access from defective memory cells to healthy replacement cells without the host knowing about the defects.
2Reliability
If weak memory cells are replaced with redundancy memory cells, then the operational reliability improves, but the repair efficiency and manufacturing yield decrease
Solution Approach 1:
The patent applies local quality by differentiating between weak memory cells and failed memory cells. Instead of uniformly replacing all defective cells with redundancy cells, the system applies targeted compensation only to weak cells that can still function with assistance, preserving manufacturing yield while improving reliability.
Solution Approach 2:
The patent changes the operational parameters of weak memory cells by adjusting read/write voltages or using error correction codes specifically for identified weak cells. This allows the cells to function reliably without physical replacement, maintaining manufacturing yield while improving operational reliability.
3Speed
If data retention characteristics decrease due to low-voltage high-speed operation, then the operation speed increases, but the number of weak memory cells increases
Solution Approach 1:
The patent implements feedback mechanisms where the memory management unit continuously monitors memory cell performance and dynamically adjusts compensation strategies. When weak cells are detected through data retention testing, the system automatically updates its mapping table and redirects access, ensuring high-speed operation continues without reliability degradation.
Data Source
AI summary
A memory system includes a memory device including a plurality of memory cells, and a memory controller suitable for generating a second address based on a first address indicating a defective memory cell, among the plurality of memory cells, and sequentially transmitting the first address and a first command corresponding to the first address, and the second address and a second command corresponding to the second address to the memory device, during write and read operations of the defective memory cell.