Memory Controller Delay Block Synchronization
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Solution Overview
Problem
In memory systems with multiple memory devices, timing skews due to variations in process/voltage/temperature conditions and environmental differences between channels lead to increased complexity and area requirements in controllers, necessitating multiple delay blocks to synchronize internal clock signals with data strobe signals, which can be inefficient.
Innovation Solution
A memory system configuration where a representative memory device outputs a representative data strobe signal, and non-representative memory devices adjust their data strobe signals through the representative device, with a controller generating an internal delay clock signal synchronized with the representative data strobe signal to control delay times, allowing phase alignment without the need for multiple delay blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple delay blocks are used to synchronize internal clock signals with data strobe signals for each memory device, then timing skew is reduced, but controller area and device complexity increase
Solution Approach 1:
The patent applies universality by designing a single delay block that serves multiple memory devices through a shared feedback mechanism. The delay block receives feedback from multiple memory devices and adjusts its delay time to synchronize with the data strobe signal from any of the memory devices, eliminating the need for separate delay blocks for each device.
Solution Approach 2:
The patent merges multiple delay block functions into a single delay block that handles synchronization for all memory devices. By combining the delay adjustment functionality into one shared component that uses feedback from multiple sources, the system reduces the total number of delay blocks required while maintaining timing accuracy across all devices.
2Manufacturing precision
If multiple delay blocks are used to synchronize internal clock signals with data strobe signals for each memory device, then timing skew is reduced, but device complexity increases
Solution Approach 1:
The delay block is designed with multi-functionality to handle synchronization for multiple memory devices simultaneously. It receives feedback signals from various memory devices and dynamically adjusts its delay time to match the data strobe signal timing, providing universal synchronization capability without requiring device-specific delay blocks.
Solution Approach 2:
The patent combines multiple synchronization functions into a single delay block that serves all memory devices. By merging the delay adjustment logic and feedback mechanisms into one integrated component, the system reduces the overall complexity of the controller while maintaining precise timing synchronization across all devices.
Data Source
AI summary
A memory system includes a representative memory device directly outputting a representative data strobe signal, at least one non-representative memory device outputting a non-representative data strobe signal through the representative memory device, and a controller generating an internal delay clock signal synchronized with the representative data strobe signal. The controller outputs a test mode code defining a delay time using the internal delay clock signal as a reference signal. The at least one non-representative memory device adjusts a phase of the non-representative data strobe signal such that the non-representative data strobe signal has a delay time corresponding to the test mode code.