Memory Controller Delay Timer for Power-Off Data Saving
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Solution Overview
Problem
Existing memory systems face data loss issues when a power disable signal is directly supplied to the power management IC, causing the memory controller to shut down unexpectedly.
Innovation Solution
The memory controller delays the power disable signal to allow sufficient time for data saving by transmitting a control signal to the power circuit, ensuring data is saved before power is turned off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PWRDIS signal is directly supplied to the PMIC, then the power output is turned off according to the signal, but the memory controller cannot save data and enters an unexpected shutdown state causing data loss
Solution Approach 1:
The memory controller performs preliminary data saving operations before the power management IC actually disables power output. The controller receives the PWRDIS signal, activates a delay timer, and uses this delay period to complete data saving operations before power is actually cut, preventing data loss.
Solution Approach 2:
The delay timer acts as an intermediary between the PWRDIS signal reception and the actual power disable action. It mediates the timing relationship by holding the power disable operation until after data saving is complete, preventing the direct coupling that causes data loss.
2Reliability
If the memory controller delays the power disable signal to save data, then data loss is prevented, but the power disable operation is postponed beyond the original signal timing
Solution Approach 1:
The system dynamically adjusts the power disable timing based on data saving requirements. The delay timer is configured with a predetermined period that provides sufficient time for data operations, and the power disable is executed dynamically after this delay expires, rather than immediately upon signal reception.
3Reliability
If additional external circuits are added to delay the power disable signal, then data saving time is secured, but the system configuration becomes more complex
Solution Approach 1:
The memory controller performs the delay function using its own internal resources - specifically, it uses an existing delay timer that is already part of its architecture. This self-service approach eliminates the need for external delay circuits while still providing the necessary data saving time.
Data Source
AI summary
According to one embodiment, a memory system includes a nonvolatile memory to store data, a memory controller configured to perform data operations on the nonvolatile member, and a power circuit configured to receive external power and generate internal power to be supplied to the nonvolatile memory and the memory controller. The memory controller is further configured to receive a request signal for disabling supply of the internal power for a first time period and disable the supply of the internal power from the power circuit in response to the request signal after a second time period elapses after reception of the request signal. The second time period is shorter than the first time period. The supply of the internal power from the power circuit resumes after the first time period elapses after the reception of the request signal.