Memory Controller Delay Training Circuit for DDR Strobe Signal
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Solution Overview
Problem
Current methods for training data strobe signals in DDR memory systems are inefficient, requiring multiple iterations at different frequencies and pre-characterized seed values, which can lead to unpredictable behavior and erroneous reads due to sampling of tri-stated data strobe signals.
Innovation Solution
A memory controller with a training circuit that adjusts the phase of an enable signal relative to the data strobe signal using a delay locked loop (DLL) to ensure the enable signal coincides with the preamble indication, thereby preventing sampling of a tri-stated data strobe signal, and storing the delay indication in a register for future operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple iterations at different frequencies are performed for training, then the data strobe signal timing may be optimized, but the training time and system complexity increase significantly
Solution Approach 1:
The patent performs training at a low frequency seed value first to establish initial timing relationships before operating at higher frequencies. This preliminary training at lower frequencies provides a foundation that simplifies subsequent high-frequency training, avoiding the need for exhaustive multi-iteration training at each frequency level.
Solution Approach 2:
The patent uses the timing relationships established at lower frequencies as a template or copy for high-frequency training. The trained timing parameters from seed frequency are reused and adapted for higher frequencies, reducing the need for complete re-training and significantly decreasing overall training time.
2Ease of operation
If pre-characterized seed values are used for training, then the training process can be initialized, but unpredictable behavior and erroneous reads may occur due to sampling of tri-stated data strobe signals
Solution Approach 1:
The patent implements a feedback mechanism where the system monitors the stability and validity of trained timing parameters. If unpredictable behavior or erroneous reads are detected, the system can adjust the training parameters or re-perform training, ensuring reliable operation before transitioning to normal high-frequency reads.
Solution Approach 2:
The patent performs comprehensive training at lower frequencies before operating at higher frequencies, creating a cushion of validated timing parameters. This preliminary training establishes robust timing relationships that prevent erroneous reads during high-frequency operation, cushioning against potential reliability issues.
3Productivity
If training is performed at higher frequencies directly, then system performance can be optimized, but training stability and predictability decrease
Solution Approach 1:
The patent performs training at a low frequency seed value first to establish initial timing relationships before operating at higher frequencies. This preliminary training at lower frequencies provides a foundation that simplifies subsequent high-frequency training, avoiding the need for exhaustive multi-iteration training at each frequency level.
Solution Approach 2:
The patent systematically changes the frequency parameter from low to high in a controlled sequence. By transitioning through intermediate frequency steps rather than jumping directly to high frequencies, the training process maintains stability while progressively achieving high-performance operation.
Data Source
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AI summary
Various method and apparatus embodiments for training a delay for enabling a data strobe signal in a memory subsystem are disclosed. In one embodiment, a system includes a memory controller configured to receive a data strobe signal. The memory controller includes a training circuit. The training circuit includes a first storage circuit coupled to receive the data strobe signal on a data input and an enable signal on a clock input, and a training unit configured to, based on an output signal received from the first flip-flop, adjust a phase of the enable signal until an assertion of the enable signal coincides with a preamble indication in the data strobe signal.