Semiconductor Memory Controller Die Asynchronous Read Latency
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Solution Overview
Problem
Existing multi-chip packages (MCPs) for semiconductor memory devices face high power consumption issues, particularly in mobile devices where battery power is limited, due to inefficient bus configurations and synchronization requirements.
Innovation Solution
A semiconductor memory device design featuring a controller die connected to multiple memory die via dedicated internal control and data buses, allowing for asynchronous read data output and reduced power consumption by disabling synchronization circuits and using on-die termination options, while maintaining deterministic latency and compliance with JEDEC standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If synchronization circuits and on-die termination are implemented in each memory die, then signal integrity and timing precision are improved, but power consumption and device complexity increase
Solution Approach 1:
The patent merges the synchronization function from individual memory die into a centralized controller die. The controller die generates and distributes synchronized clocks to multiple memory die, eliminating the need for each memory die to have its own synchronization circuit. This consolidation maintains timing precision while reducing power consumption and complexity in the memory die.
Solution Approach 2:
The patent extracts the synchronization circuit functionality from each memory die and relocates it to a dedicated controller die. This separation allows the memory die to operate without complex synchronization circuits, reducing their power consumption and complexity, while the controller die handles all synchronization tasks centrally.
2Productivity
If dedicated internal buses are provided to each memory die, then parallel operation and bandwidth are improved, but power consumption and device complexity increase
Solution Approach 1:
The patent implements a dynamic bus sharing mechanism where the internal control bus is selectively connected to different memory die based on operational needs. The controller die can establish dedicated connections to individual memory die or groups of memory die as required, enabling parallel operations when needed while allowing bus resources to be shared and deactivated otherwise, thus balancing bandwidth requirements with power consumption.
3Quantity of substance
If multiple memory die are integrated in a single package, then density is improved, but power consumption and heat generation increase
Solution Approach 1:
The patent segments the memory system into a controller die and multiple memory die, each with simplified functionality. The controller die handles all complex control, synchronization, and termination functions, while the memory die focus solely on data storage and retrieval. This segmentation allows the memory die to be powered down or placed in low-power states more easily, reducing overall power consumption while maintaining high density through the multi-die package architecture.
Data Source
AI summary
A semiconductor memory device including a plurality of memory die and a controller die. The controller die is connected to an internal control bus. The controller die is configured to provide to a selected one of the memory die an internal read command responsive to an external read command. The selected memory die is configured to provide read data to the controller in response to the internal read command; wherein latency between receipt by the controller die of the external read command and receipt of the read data from the selected memory die differs for at least two of the memory die when selected as the selected memory die.