Memory Controller Division Tracking Read for NAND Flash
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Solution Overview
Problem
NAND flash memory systems face challenges in accurately reading data due to changes in word line resistance caused by defects, leading to suboptimal read voltages and increased error bits, especially in three-dimensional stacked structures where defects can alter the effective threshold voltage distribution.
Innovation Solution
The memory system employs a division tracking read method, where the memory controller applies a series of read voltages to each region of the memory cell array to estimate an optimal read voltage for each segment, improving data retrieval accuracy by adjusting read voltages based on regional resistance changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single read voltage is applied to the entire memory cell array, then the read operation is simple and fast, but reading accuracy deteriorates due to regional resistance variations caused by defects
Solution Approach 1:
The memory cell array is divided into multiple regions, and a division tracking read is performed for each region separately. This segmentation allows the system to apply region-specific read voltages that account for local resistance variations caused by defects, thereby improving reading accuracy without requiring a complete redesign of the read operation architecture.
Solution Approach 2:
Different read voltages are applied to different regions of the memory cell array based on their specific characteristics. The system estimates the optimal read voltage for each region by tracking the threshold voltage distribution locally, ensuring that each region is read with the most appropriate voltage for its conditions, thus improving overall reading accuracy.
2Measurement precision
If read voltage is optimized for each region, then data retrieval accuracy improves, but the time required for read operations increases
Solution Approach 1:
The system performs a tracking read operation beforehand to estimate the threshold voltage distribution and determine the optimal read voltage for each region. This preliminary action allows the main read operation to proceed efficiently with pre-determined optimal voltages, reducing the time penalty associated with region-specific optimization.
Solution Approach 2:
The division tracking read focuses on estimating the threshold voltage distribution in a simplified manner rather than performing a complete and precise analysis. By using a partial action approach that captures the essential characteristics without exhaustive measurement, the system achieves sufficient accuracy while minimizing the time overhead.
3Reliability
If defects are present in the memory cell array, then manufacturing yield is reduced, but the system can still salvage data through adaptive read voltage adjustment
Solution Approach 1:
The system performs a tracking read to measure the actual threshold voltage distribution in each region, then uses this feedback information to adjust the read voltage for subsequent data retrieval operations. This feedback mechanism enables the system to adapt to defects and variations in the memory cell array, salvaging data that would otherwise be unreadable due to manufacturing imperfections.
Solution Approach 2:
The system dynamically changes the read voltage parameter based on the detected threshold voltage distribution in each region. By adjusting this critical parameter according to actual conditions rather than using a fixed voltage, the system can compensate for defects and maintain reliable data retrieval even when manufacturing precision is compromised.
Data Source
AI summary
A memory system includes a semiconductor memory and a memory controller. The semiconductor memory includes first memory cells, first bit lines connected to the first memory cells, second memory cells, second bit lines connected to the second memory cells, a word line connected to the first and second memory cells, and a driver configured to apply a voltage to the word line. In response to a special read command from the memory controller, the driver sequentially applies, to the word line, first read voltages to read data from the first memory cells, a second read voltage within a voltage range of the first read voltages to read data from the first memory cells, third read voltages to read data from the second memory cells, and a fourth read voltage within a voltage range of the third read voltages to read data from the second memory cells.