Memory Controller Dynamic Latency Aware Write Scheduling
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Solution Overview
Problem
DDR memory systems face inefficiencies due to the overhead of turning around the memory bus from write to read accesses, leading to increased read latency and reduced memory controller efficiency.
Innovation Solution
The implementation of dynamic latency aware write (DLAW) picking, where the memory controller elevates the priority of older write accesses in the command queue when a read command is detected for the same memory region, allowing earlier issuance of read cycles and reducing average read latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the memory controller prioritizes read accesses before write accesses to avoid stalling the data processor, then read latency is reduced, but memory controller efficiency deteriorates due to the overhead of turning around the memory bus from writes to reads
Solution Approach 1:
The memory controller performs preliminary actions by detecting read accesses in advance and elevating the priority of older write accesses to the same memory region before the read is executed. This allows the write accesses to be issued earlier, reducing the turnaround overhead and enabling the read to proceed with lower latency while maintaining overall controller efficiency.
Solution Approach 2:
The arbitration priority of write accesses is made dynamic rather than static. The priority of older write accesses is elevated conditionally when a read access to the same memory region is detected, allowing the system to adapt to specific access patterns and reduce turnaround overhead only when beneficial, rather than always prioritizing reads.
2Loss of time
If the memory controller issues read accesses immediately to reduce read latency, then read latency is improved, but memory bus turnaround overhead increases
Solution Approach 1:
The system performs preliminary detection of read accesses and elevates write priorities in advance, allowing writes to be issued before the read executes. This preliminary action reduces the turnaround overhead by ensuring writes are completed or queued appropriately before the read accesses the memory bus, reducing energy waste from bus switching.
3Reliability
If the memory controller maintains strict FIFO ordering for write accesses, then write access reliability is improved, but read latency increases due to inability to interleave reads and writes
Solution Approach 1:
The arbitration scheme dynamically adjusts priorities based on access type and timing. Writes maintain their relative ordering through the elevation mechanism (older writes get elevated priority), while reads can be inserted by triggering write priority elevations. This dynamic approach preserves write reliability while enabling read latency reduction through strategic interleaving.
Solution Approach 2:
The system uses feedback from detected read accesses to adjust write arbitration priorities. When a read is detected, the system feeds back information about older writes to the same memory region, causing their priorities to be elevated. This feedback mechanism enables intelligent interleaving that maintains write ordering while reducing read latency.
Data Source
AI summary
A memory controller includes a command queue that receives and stores decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command, and an arbiter coupled to the command queue and picks selected decoded memory commands among the decoded memory commands from the command queue for dispatch to the memory system by comparing the priority and the age for decoded memory commands having a first type. The arbiter detects when the command queue receives a decoded memory command of a second type opposite to said first type that accesses a first memory region of the memory system, and in response performs at least one pre-work action that reduces a latency of the decoded memory command of the second type.