Memory Controller Accessing DRAM Devices with Different Bit-Widths
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Solution Overview
Problem
Conventional memory controllers face design flexibility issues when trying to access DRAM devices with different output bit-widths and memory bank configurations, as they typically require the same bit-width and number of memory banks to use the same control command, limiting their ability to simultaneously access DRAM devices with 8-bit and 16-bit output bit-widths.
Innovation Solution
A memory controller design that generates specific signals to select memory bank groups for DRAM devices with different bit-widths, allowing simultaneous access by utilizing bank group signals as part of address signals and ensuring logical value correspondence between active and access phases, thereby accommodating different memory bank group configurations without violating DDR4 standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a memory controller is designed to access DRAM devices with the same bit-width and memory bank configuration, then control command consistency is maintained, but the ability to simultaneously access DRAM devices with different output bit-widths and memory bank configurations is lost
Solution Approach 1:
The patent segments the control approach by separating the handling of different DRAM device types. It introduces separate control paths: one for accessing DRAM devices with the same configuration (using standard control commands) and another for accessing DRAM devices with different configurations (using converted control commands). This segmentation allows the memory controller to maintain simplicity for common cases while gaining flexibility for diverse device types.
Solution Approach 2:
The memory controller is designed with multi-functionality to handle both uniform and diverse DRAM device configurations. It can operate in two modes: a standard mode for accessing multiple DRAM devices with identical bit-width and memory bank configurations, and a flexible mode for accessing DRAM devices with different configurations by converting control commands appropriately. This universal design resolves the contradiction between maintaining control consistency and achieving adaptability.
2Adaptability or versatility
If DRAM devices with different output bit-widths are coupled to the same memory controller, then design flexibility is improved, but timing parameter limitations during memory bank group switching occur
Solution Approach 1:
The patent applies preliminary action by performing control command conversion in advance before the actual access operation. When a memory access request is made to DRAM devices with different configurations, the controller pre-converts the control commands into appropriate forms for each target device type. This preliminary conversion ensures that timing parameters are properly adjusted before execution, preventing timing conflicts during memory bank group switching while maintaining design flexibility.
3Ease of operation
If standard control commands are used for all DRAM devices, then ease of control is maintained, but the ability to accommodate different memory bank group configurations is lost
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of a control command conversion unit. This intermediary sits between the standard control command interface and the diverse DRAM device configurations. When control commands are issued, the intermediary automatically converts them into the appropriate forms for the target DRAM devices, whether they have the same or different memory bank group configurations. This intermediary preserves ease of operation for the controller while enabling broad adaptability to different device types.
Data Source
AI summary
A method for simultaneously accessing a first DRAM device and a second DRAM device includes the steps of: in an active phase, generating a first signal at a first pad, wherein the first signal is provided for the first DRAM device to select a first memory bank group, and the first signal is not for the second DRAM device to select any memory bank group; and generating a second signal at the first pad, wherein the second signal is provided for the first DRAM device to select the first bank group, and the second signal and the first signal correspond to a same digital value.