Memory Controller Command Issuance Order for DRAM Penalty Reduction
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Solution Overview
Problem
The existing methods for writing data of less than a predetermined length into DRAM, such as the LPDDR4 standard, incur a significant penalty due to the longer interval required for issuing subsequent write commands, which can lead to unintentional data overwrite or increased write data, and are not applicable to partial write operations.
Innovation Solution
A memory controller that issues a first write command for data of a predetermined length and a second write command for data less than that length, with a deciding unit that optimizes the issuance order of DRAM commands to reduce the penalty by allowing other commands to be issued before the second write command, thereby improving access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an MWR command is issued to write data of less than a predetermined length into DRAM, then the write operation can be performed with simplified control, but a long penalty period is incurred requiring a four times longer interval before the next command can be issued
Solution Approach 1:
The memory controller issues commands to different banks before the penalty period of an MWR command completes. By preparing and queueing commands for other banks in advance, the system utilizes the penalty time productively rather than waiting idle, thereby reducing the overall impact of the long penalty period on performance.
Solution Approach 2:
The system dynamically adjusts command issuance based on bank state and penalty conditions. When an MWR command is detected, the controller identifies which banks are affected and dynamically reorders the command queue to issue commands to unaffected banks during the penalty period, optimizing throughput adaptively.
2Loss of time
If a WR command is used instead of MWR command for partial writes, then the penalty period is reduced, but data may be unintentionally overwritten or write data amount may increase
Solution Approach 1:
The memory controller applies different control strategies to different banks based on their operational state. When a bank is in a penalty state due to an MWR command, the controller selectively issues commands to other banks that are not affected, applying localized optimization without compromising data integrity in the affected bank.
Solution Approach 2:
The controller continuously monitors the execution state of commands and tracks penalty periods. Based on this feedback, it dynamically adjusts the command issuance timing and ordering to ensure that commands are issued only when safe, preventing data overwrite while maximizing throughput.
3Device complexity
If commands are issued sequentially in the original order, then command processing is simple, but DRAM access efficiency is reduced due to the long penalty period of MWR commands
Solution Approach 1:
The memory controller issues commands to different banks before the penalty period of an MWR command completes. By preparing and queueing commands for other banks in advance, the system utilizes the penalty time productively rather than waiting idle, thereby reducing the overall impact of the long penalty period on performance.
Solution Approach 2:
The system dynamically adjusts command issuance based on bank state and penalty conditions. When an MWR command is detected, the controller identifies which banks are affected and dynamically reorders the command queue to issue commands to unaffected banks during the penalty period, optimizing throughput adaptively.
Data Source
AI summary
A memory controller that is formed to be able to issue a first write command for writing data of a predetermined length into a DRAM and a second write command for writing data which is less than the predetermined length in the DRAM is provided. The memory controller comprises a deciding unit configured to decide an issuance order of a request stored in the storage unit. In a period from the issuance of a preceding DRAM command until a second write command targeting the same bank as the preceding DRAM command is issued, if another DRAM command targeting a bank different from the bank targeted by the preceding DRAM command can be issued, the deciding unit will decide the issuance order so that the other DRAM command that can be issued will be issued before the second write command.