Memory Controller Request Reordering for DRAM Access Efficiency
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Solution Overview
Problem
Existing memory controllers face challenges in maximizing DRAM access performance due to page misses and switching between reading and writing, leading to increased complexity in reordering logic circuits and decreased access efficiency.
Innovation Solution
A memory controller with a first storage unit for storing requests with priority and access type information, a first control unit for selecting requests based on these criteria, and a second storage unit for rearranging requests to generate DRAM commands, prioritizing high-priority access types, thereby reducing DRAM access penalties and minimizing reordering circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel DRAM command generation is implemented to reduce access penalties, then access performance is improved, but reordering logic circuit area increases exponentially
Solution Approach 1:
The patent segments the reordering process into multiple stages with dedicated request buffers at each stage. Instead of generating all DRAM commands in parallel from a single buffer, the system divides the reordering logic into sequential stages that process requests progressively, reducing the complexity and area of individual logic circuits while maintaining overall access performance.
Solution Approach 2:
The patent introduces a multi-dimensional approach by adding stage numbering and hierarchical buffer structures. Requests are tracked across multiple dimensions (stage, buffer position, request type) rather than relying solely on complex parallel logic, thereby reducing circuit area while achieving effective reordering.
2Device complexity
If only page miss is considered for reordering, then logic circuit complexity is reduced, but access efficiency decreases due to frequent reading-writing switching
Solution Approach 1:
The patent applies different reordering strategies to different request types locally. The system identifies specific access patterns (reading-writing switching, sequential access, random access) and applies targeted reordering rules for each pattern rather than using a single complex global reordering logic, thereby reducing overall circuit complexity while maintaining access efficiency.
Solution Approach 2:
The patent changes the parameters considered for reordering beyond just page misses. It incorporates access type (read/write), access pattern (sequential/random), and stage information as additional parameters, enabling more efficient reordering decisions with simpler logic by considering multiple factors simultaneously rather than relying on complex single-parameter logic.
3Productivity
If more request buffer stages are added to improve reordering, then access performance is improved, but reordering logic circuit area increases
Solution Approach 1:
The patent segments the request buffer into multiple stages, where each stage handles a portion of the reordering process. This segmentation allows the system to achieve effective reordering across multiple buffer stages without requiring exponentially increasing logic circuit area, as each stage uses simplified logic that builds upon the previous stage's work.
Data Source
AI summary
A memory controller for controlling DRAM, comprising: a first storage unit configured to store requests that each comprise information about a priority and an access type received by the memory controller; a first control unit configured to select requests from the requests; a second storage unit configured to store the selected requests; and a second control unit configured to rearrange the requests stored in the second storage unit to generate a DRAM command and to issue the DRAM command to the DRAM, wherein the second control unit generates a priority access type indicating which access type request to preferentially issue to the DRAM, and the first control unit selects the requests, based on the information about the priority and the access type of each of the requests stored in the first storage unit, and the priority access type.