Memory Controller Drift Compensation for Read Reliability
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Solution Overview
Problem
The threshold voltage of memory cells drifts over time, leading to read margin loss and Uncorrectable Error Correction Code (UECC), as existing technologies fail to account for the drift, reducing the reliability of data stored in memory systems.
Innovation Solution
A memory system and method that includes a memory controller which checks if a logical block address is in a write buffer, determines the level of drift, and sends a read command based on this level, with processes performed in parallel to improve read operation reliability and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the threshold voltage drift of memory cells is not considered, then the read operation is simple and fast, but the read command may fail and data reliability is reduced
Solution Approach 1:
The patent applies preliminary action by determining the drift level of the logical block address before executing the read command. The memory controller checks whether the logical block address is maintained in the write buffer, and if not, determines the drift level in advance. This preliminary determination of drift level allows the system to select appropriate read voltage levels before the actual read operation, preventing read failures and ensuring data reliability without adding complexity during the read execution itself.
2Productivity
If multiple processes are performed sequentially, then the system is simple to implement, but the read latency is increased and reading efficiency is reduced
Solution Approach 1:
The patent applies segmentation by dividing the read operation into multiple independent processes that can be executed in parallel: (1) checking whether the logical block address is maintained in the write buffer, (2) determining the drift level of the logical block address, and (3) sending the read command to the non-volatile memory device. These segmented processes are implemented using multiple processors (first processor for buffer checking, second processor for drift determination, third processor for command transmission), allowing simultaneous execution and reducing overall read latency while improving reading efficiency.
3Measurement precision
If the drift level is determined based on data heat, then the read voltage selection is more accurate, but the processing time is increased
Solution Approach 1:
The patent applies preliminary action by pre-determining the drift level based on data heat classification before the actual read operation. The memory controller classifies data into hot, warm, and cold categories based on access patterns, and determines the corresponding drift levels in advance. This preliminary classification and drift level determination allows the system to quickly select appropriate read voltages during subsequent read operations, achieving accurate drift measurement without significant processing time penalty.
Data Source
AI summary
In an example, a memory controller is configured to: check whether a logical block address corresponding to a host read command is maintained in a write buffer; determine a level of an amount of drift corresponding to the logical block address if the logical block address is not maintained in the write buffer, where different levels of the amount of drift correspond to different read voltages; and send a read command to a non-volatile memory device according to the level of the amount of drift corresponding to the logical block address. At least two of the processes of checking whether the logical block address is maintained, determining the level of the amount of drift, or sending the read command are performed in parallel.