Memory Controller Command Latency Reduction via Dual-Edge Arbitration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory controllers face challenges in reducing command latency and maintaining command bandwidth due to logic intensiveness and timing constraints, particularly at advanced technology nodes like 90 nm, where fitting arbitration and page management logic within a single clock cycle is difficult, and moving to faster nodes or pipelining commands can compromise performance.
Innovation Solution
Operating the arbitration logic of a memory controller at a core clock frequency lower than the memory clock frequency, parallelizing commands based on timing requirements, and synchronizing them using a phase-shifted mask to ensure availability at the memory clock frequency, thereby reducing latency and maintaining bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory clock frequency is increased to 800 MHz for higher performance, then the command bandwidth is improved, but the command latency increases and timing closure becomes difficult
Solution Approach 1:
The patent segments the command issuance process into multiple parallel streams by utilizing both rising and falling edges of the core clock cycle. Instead of issuing commands sequentially in a single clock domain, the system divides command generation into parallel paths that can operate simultaneously, effectively halving the latency while maintaining bandwidth at 800 MHz.
Solution Approach 2:
The patent transitions from a single-dimension sequential command issuance (one command per clock cycle) to a multi-dimensional parallel command issuance by exploiting both rising and falling edges of the clock cycle. This dimensional expansion allows two commands to be issued per core clock cycle, reducing latency without sacrificing bandwidth.
2Device complexity
If all page management and arbitration logic is fitted into a single clock cycle, then the device complexity is reduced, but it becomes impossible to meet timing requirements at 800 MHz
Solution Approach 1:
The patent segments the complex arbitration and page management logic into separate stages that operate in parallel. By dividing the logic into distinct functional blocks (arbitration logic, page management logic, command generation logic) that can work simultaneously on different clock edges, the system achieves timing closure at 800 MHz while maintaining comprehensive functionality.
Solution Approach 2:
The patent performs preliminary arbitration and page management decisions at the lower core clock frequency before command issuance. By resolving conflicts and determining command sequences in advance at the relaxed core clock timing, the system prepares commands that can be rapidly issued at the 800 MHz memory clock rate without compromising timing closure.
3Reliability
If pipelining is used to sequence commands over multiple clock cycles, then the logic timing requirements are met, but the command latency is compromised
Solution Approach 1:
The patent implements periodic parallel command issuance by utilizing both rising and falling edges of the core clock cycle. This periodic dual-edge operation allows commands to be issued at twice the frequency of traditional single-edge pipelines, reducing latency while maintaining the structured sequencing needed for timing compliance through the phase-shifted mask mechanism.
Data Source
AI summary
A method includes operating an arbitration logic of a memory controller at a core clock frequency lower than that of a memory clock frequency. The memory controller is configured to generate a command sequence including a number of commands in accordance with a number of external requests to access the memory. The method also includes parallelizing the number of commands in the command sequence based on a timing requirement for a non-first command in the command sequence defined by a memory-access protocol being satisfied at a rising edge or a falling edge of the core clock relative to a previous command in the command sequence. Further, the method includes ensuring, through the parallelizing, availability of the number of commands in the command sequence to a memory interface operating at the memory clock frequency at a command rate equal to the memory clock frequency.