Memory Controller Dual Interface Protocol Switching
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Solution Overview
Problem
Existing memory controllers lack the ability to seamlessly communicate with external hosts using different protocols, limiting their applicability and compatibility across various devices.
Innovation Solution
A memory controller design that incorporates both an embedded multimedia card (eMMC) interface and a universal flash storage (UFS) interface, utilizing a specific pin to switch between protocols based on a clock signal level, allowing communication with external hosts via either eMMC or UFS protocols depending on the pin level, thereby increasing compatibility and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a memory controller supports multiple communication protocols (eMMC and UFS), then adaptability and versatility are improved, but device complexity increases
Solution Approach 1:
The memory controller is designed with dual transmittal modules (first transmittal module for eMMC protocol and second transmittal module for UFS protocol) that share common resources including the clock pin and specific pin. This multi-functionality allows a single controller to support multiple communication protocols without requiring completely separate communication paths for each protocol, thereby improving adaptability while controlling complexity.
Solution Approach 2:
The controller dynamically switches between eMMC and UFS protocols based on the signal level detected on the specific pin. When the specific pin is at a first level, the controller operates in eMMC mode; when at a second level, it operates in UFS mode. This dynamic protocol selection allows the controller to adapt to different communication requirements without maintaining permanent dual-mode operation, reducing overall system complexity.
2Adaptability or versatility
If dual transmittal modules are implemented for protocol switching, then adaptability is improved, but power consumption increases
Solution Approach 1:
The controller employs dynamic protocol selection where only one transmittal module is actively used at any given time based on the specific pin level. The controller monitors the specific pin and activates either the first transmittal module (eMMC) or the second transmittal module (UFS) accordingly, ensuring that the inactive module remains in a low-power state. This dynamic activation strategy enables protocol adaptability while minimizing power consumption by avoiding simultaneous operation of both modules.
3Ease of operation
If protocol switching is implemented via pin level detection, then ease of operation is improved, but device complexity increases
Solution Approach 1:
The memory controller automatically detects the required communication protocol by monitoring the signal level on the specific pin without requiring external intervention or configuration. The controller's internal logic autonomously determines whether to operate in eMMC or UFS mode based on the detected pin level, and seamlessly switches between protocols as needed. This self-service capability simplifies operation for the user while the control logic manages the complexity internally.
Data Source
AI summary
A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level.