Memory Controller Dummy Command Dispatch for Batch Read Error Handling

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Solution Overview

Problem

In storage systems with nonvolatile memory, existing memory controllers face inefficiencies in data transfer and error handling during batch operations, leading to increased overhead and potential malfunctions due to incomplete error correction and inaccurate reporting of command completion.

Innovation Solution

The implementation of a memory controller architecture that includes a write controller issuing batch commands, a command dispatcher, and a memory interface, where dummy commands are used to ensure accurate reporting of batch command completion even in the presence of read errors, by differentiating between actual and dummy commands and handling error corrections separately.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a memory controller issues one command including multiple read commands for batch operations, then data transfer efficiency is improved, but error handling becomes complex and completion reporting becomes inaccurate

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoiderror handling accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the batch command processing by introducing a command dispatcher that separates dummy commands from actual read commands. This segmentation allows the system to track and report completion status accurately for each command type, resolving the contradiction between batch processing efficiency and error handling accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The command dispatcher acts as an intermediary between the memory controller and the memory interface. It receives batch commands, generates dummy commands, and manages the sequencing and reporting of command completions. This intermediary layer enables accurate completion reporting while maintaining batch processing efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If dummy commands are added to ensure accurate completion reporting, then system reliability is improved, but command processing overhead increases

Engineering Contradiction:
Improvecompletion reporting accuracyVSAvoidcommand processing overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The command dispatcher generates dummy commands in advance as part of the batch command processing. This preliminary action ensures that completion reporting can be accurately tracked without adding complex error handling logic during execution, thus improving reliability while managing overhead.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes the parameter of command sequencing by interleaving dummy commands with actual read commands. This parameter change allows the memory interface to receive commands in a controlled sequence, enabling accurate completion reporting without significantly increasing processing overhead.

Inventive Principle:
Principle #35Parameter changes

3Difficulty of detecting and measuring

If read commands are executed sequentially in batch operations, then error detection becomes easier, but processing speed decreases

Engineering Contradiction:
Improveerror detection easeVSAvoidprocessing speed
Core Design Contradiction:
Difficulty of detecting and measuringVSSpeed

Solution Approach 1:

The command dispatcher implements a feedback mechanism where the memory interface reports completion status of each command (including dummy commands) back to the command dispatcher. This feedback allows errors to be detected systematically while maintaining batch processing speed through parallel command execution.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system maintains continuous useful action by executing multiple read commands in batch while the command dispatcher continuously manages dummy command insertion and completion tracking. This continuity ensures both processing speed is maintained and error detection remains systematic through the feedback loop.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS9904609B2Memory controller and memory device
Publication Date: 2018.02.27 KIOXIA CORP
  • US9904609B2 patent drawing
  • US9904609B2 patent drawing
  • US9904609B2 patent drawing

AI summary

According to one embodiment, a memory controller includes a first controller issuing one command which includes read commands for reading data from a nonvolatile memory, a second controller sequentially issuing the read commands and a dummy command which continues the read commands when the one command is received, and a third controller sequentially executing the read commands and the dummy command and informing an information of a read error to the second controller when the read error occurred, the second controller informing a completion of the one command to the first controller when the command which corresponds to the read error is the dummy command.