Memory Controller Dummy Pulse Sequencing for Voltage Noise
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Solution Overview
Problem
Existing memory controllers face challenges in managing sudden changes in total current consumption by memory devices, which can lead to noise in the voltage source and affect the reliability of operations.
Innovation Solution
A memory controller that applies a dummy pulse sequentially to channels coupled to memory devices to gradually increase or decrease the total current consumption, thereby preventing sudden changes and noise in the voltage source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory devices are activated simultaneously to increase productivity, then operation speed is improved, but sudden current consumption changes cause voltage noise that deteriorates reliability
Solution Approach 1:
The memory controller applies dummy pulses to memory devices before activating them for actual operations. This preliminary action gradually increases current consumption, preventing sudden changes that cause voltage noise, while still enabling subsequent high-speed operations
Solution Approach 2:
The memory controller uses periodic dummy pulses with controlled frequencies to gradually activate memory devices. This periodic activation pattern allows current consumption to increase in a controlled manner, avoiding sudden spikes that would create voltage noise
2Reliability
If dummy pulses are applied to all channels simultaneously to increase current gradually, then voltage stability is improved, but device complexity increases
Solution Approach 1:
The memory controller divides channels into multiple groups and applies dummy pulses to each group sequentially rather than simultaneously. This segmentation reduces the peak current increase rate while maintaining voltage stability, and simplifies control logic compared to individual channel management
3Use of energy by moving object
If clock signal frequency is reduced to decrease current consumption, then power usage is improved, but operation speed deteriorates
Solution Approach 1:
The memory controller dynamically adjusts the clock signal frequency based on the current operational state. During dummy pulse phases, a lower frequency is used to control current consumption, while during actual data operations, the frequency is increased to maintain high-speed performance
Data Source
AI summary
A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.