Memory Controller Duplicate Address Prevention
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Solution Overview
Problem
In memory systems, there is a challenge in preventing data corruption due to duplicate allocation of physical addresses during write operations, which can lead to errors and data loss, especially in nonvolatile memory devices like flash memory.
Innovation Solution
A memory system that includes a controller capable of converting logical addresses into virtual and then physical addresses, performing error checking to ensure unique allocation of physical addresses before writing data, using lists to manage open blocks and prevent duplicate allocations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If address mapping is performed during write operations in nonvolatile memory devices, then data storage capability is improved, but data corruption due to duplicate physical address allocation occurs
Solution Approach 1:
The patent performs address mapping and error checking operations before the actual write operation. The controller converts logical addresses to physical addresses and checks for duplicate allocations in advance, preventing data corruption before it can occur during the write process
Solution Approach 2:
The patent introduces an intermediary error checking mechanism between address conversion and data writing. This intermediary layer verifies the uniqueness of physical addresses before allowing data to be written, acting as a mediator that prevents direct corruption from duplicate address allocation
2Reliability
If error checking operations are performed before write operations, then data integrity is improved, but operation time increases
Solution Approach 1:
The error checking is performed as a preliminary action before the main write operation, allowing the system to detect and handle address errors early. This prevents wasted time on subsequent operations if errors are detected, and enables parallel processing of multiple address checks
3Measurement precision
If logical address conversion to physical address is performed, then address mapping accuracy is improved, but device complexity increases
Solution Approach 1:
The address mapping process is segmented into distinct steps: logical address reception, conversion to physical address, error checking for duplicate allocation, and finally write operation. This segmentation allows each step to be independently optimized and managed, reducing overall system complexity
Solution Approach 2:
The patent introduces an intermediary error checking layer between address conversion and write operation. This intermediary mechanism simplifies the overall system by providing a clear separation of concerns, where address conversion and error checking are handled as distinct, manageable functions
Data Source
AI summary
An operating method of a memory system that includes a memory device including a plurality of blocks and a controller including a memory in which a first open block list and a second open block list are stored, the method comprising receiving a write request and a logical address from a host; converting the logical address into a first virtual address; converting the first virtual address into a physical address; performing a first error checking operation of checking a mapping relationship between the first virtual address and the physical address based on the first open block list; performing a second error checking operation of checking whether the physical address is included in the second open block list; and performing a write operation on an open block corresponding to the physical address when it is determined that the physical address is not allocated more than once.