Memory Controller Duty Cycle Correction for NAND Bus Signal Integrity
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Solution Overview
Problem
Memory systems face challenges in maintaining optimal duty cycles for read enable and data strobe signals due to parasitic capacitance in the NAND bus, leading to signal distortion and failure to meet specifications.
Innovation Solution
A memory controller with a duty cycle correction mechanism, including a duty cycle corrector circuit, detection circuit, and selector circuit, adjusts the duty cycles of read enable and data strobe signals using a correction code to ensure they fall within specific regions, thereby maintaining signal integrity and meeting specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read enable and data strobe signals are transmitted through the NAND bus, then data can be read from the semiconductor memory, but parasitic capacitance causes signal distortion and duty cycle deviation from specifications
Solution Approach 1:
The patent applies preliminary action by detecting the duty cycle of the data strobe signal before it is used for data reading, and preemptively adjusting it to the correct value. The duty cycle detection circuit measures the actual duty cycle, and the duty cycle correction circuit pre-adjusts the signal to compensate for parasitic capacitance effects before the signal is used for normal operation, ensuring specification compliance.
Solution Approach 2:
The patent implements feedback by using the duty cycle detection circuit to continuously monitor the duty cycle of the data strobe signal and feed this information back to the duty cycle correction circuit. The correction circuit then adjusts the signal based on the detected duty cycle value, creating a closed-loop control system that maintains duty cycle accuracy despite parasitic capacitance variations.
2Manufacturing precision
If duty cycle correction is implemented to meet specifications, then signal quality improves, but additional circuits are required in the memory controller
Solution Approach 1:
The patent applies merging by integrating the duty cycle detection and correction functions directly into the existing memory controller architecture. The duty cycle detection circuit and correction circuit are combined with the normal control signal generation pathways, allowing duty cycle adjustment to be performed using existing controller resources without requiring completely separate independent systems.
Solution Approach 2:
The patent implements universality by designing the duty cycle correction mechanism to handle multiple signal types (read enable signals and data strobe signals) through a unified correction approach. The same detection and correction circuits are used for different signal types, making the solution broadly applicable to various signaling scenarios within the memory interface without requiring dedicated circuits for each signal type.
Data Source
AI summary
A memory system may include a semiconductor memory and a memory controller. The memory controller may include an adjustment circuit configured to receive a first signal having a first duty cycle, and intermittently output a second signal to an outside of the memory controller on the basis of a control signal, the second signal having a second duty cycle which is different from the first duty cycle. The memory controller may further include a selector circuit configured to receive the second signal, receive a third signal which is generated on the basis of the second signal, and output a selected one of the second signal and the third signal. The memory controller may further include a control circuit configured to generate the control signal on the basis of the selected one of the second signal and the third signal output from the selector circuit.