Memory Controller Duty Ratio Adjustment Circuit
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Solution Overview
Problem
In semiconductor memories like NAND flash, the duty ratio of clock signals is often shifted due to propagation through receiver, repeater, and level shifter circuits, leading to disturbances in high-speed data reading and incorrect data reception by the controller.
Innovation Solution
A memory system with a controller that includes a duty ratio detection circuit to measure and adjust the duty ratio of clock signals, using circuits with inverters, capacitors, and resistors to synchronize the clock signals and maintain a 50:50 high-to-low level period ratio, ensuring accurate data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed data reading is implemented using both rising and falling edges of clock signals, then data transfer speed is improved, but duty ratio shift in clock signals causes reading disturbances and data reception errors
Solution Approach 1:
The patent applies preliminary action by detecting the duty ratio of the clock signal before using it for high-speed data reading. The duty ratio detection circuit measures the clock signal characteristics in advance, and the controller adjusts its operation based on this pre-detected information, ensuring reliable data reading while maintaining high transfer speed
Solution Approach 2:
The patent implements feedback by using the duty ratio detection circuit to continuously monitor the clock signal and providing this information back to the controller. The controller then adjusts its data reading operations based on the detected duty ratio, creating a closed-loop system that maintains data reading accuracy despite variations in clock signal characteristics
Data Source
AI summary
According to one embodiment, a memory system includes a first semiconductor memory and a controller. The first semiconductor memory receives a first clock, and outputs, in accordance with the first clock, a second clock and a data signal in synchronization with the second clock. The controller includes a detection circuit which detects a shift of a duty ratio of the second clock which is output from the first semiconductor memory. The controller also includes an adjustment circuit which adjusts a duty ratio of the first clock based on the shift detected by the detection circuit.