Memory Controller Dynamic Decoding for Page-Level Error Variation

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Solution Overview

Problem

Conventional memory sub-systems waste resources by applying a one-size-fits-all decoding approach to all pages of data, even though pages within the same block age at different rates, leading to inefficient error correction.

Innovation Solution

A memory sub-system controller dynamically adjusts the decoding process based on the read bit error rate (RBER) of each page, using less complex decoding for pages with lower RBER and more complex decoding for pages with higher RBER, thereby optimizing resource usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a one-size-fits-all decoding approach is applied to all pages, then decoding coverage is complete, but resource consumption increases and efficiency decreases

Engineering Contradiction:
Improvedecoding efficiencyVSAvoidresource consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent applies different decoding processes to different portions of data based on their specific characteristics. Pages are divided into first portions and second portions, where first portions undergo initial decoding and second portions undergo additional decoding only when necessary (when RBER exceeds threshold). This local differentiation optimizes resource usage by applying complex decoding only where needed rather than uniformly to all data.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The decoding process is made dynamic by adjusting the decoding strategy based on real-time RBER measurements. The system transitions from a static one-size-fits-all approach to a dynamic approach where the decoding process adapts to the actual error conditions of each page, applying additional decoding iterations only when the error rate justifies the extra resource consumption.

Inventive Principle:
Principle #15Dynamics

2Reliability

If complex decoding is applied to all pages, then error correction reliability improves, but processing time increases

Engineering Contradiction:
Improveerror correction reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements partial decoding action by applying the full complex decoding process only to the extent necessary. First portions of data receive initial decoding, and only second portions where RBER exceeds the threshold receive additional decoding. This partial application of complex decoding maintains reliability for problematic pages while avoiding unnecessary processing time for pages that are already within acceptable error margins.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If dynamic decoding adjustment is implemented, then resource efficiency improves, but system complexity increases

Engineering Contradiction:
Improveresource efficiencyVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system performs preliminary actions by first applying initial decoding to all pages and measuring RBER before deciding whether additional decoding is needed. This preliminary assessment allows the system to efficiently identify which pages require further processing, avoiding the need for complex real-time decision-making during the decoding process itself and simplifying the overall system architecture.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12107602B2Dynamic decoding for memory systems
Publication Date: 2024.10.01 MICRON TECHNOLOGY INC
  • US12107602B2 patent drawing
  • US12107602B2 patent drawing
  • US12107602B2 patent drawing

AI summary

Aspects of the present disclosure configure a system component, such as memory sub-system controller, to dynamically decode read data for zone-based memory allocations. The memory sub-system controller reads an entire memory block or zone. The memory sub-system controller decodes a first portion of the memory block or zone using a first decoding process. The memory sub-system controller determines that a second portion of the memory block or zone satisfies a criterion. In response, the memory sub-system controller applies a second decoding process to decode the second portion.