Memory Controller Dynamic Timing Adjustment
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Solution Overview
Problem
As semiconductor devices operate at increasing speeds, the skew between clock, data strobe signal, and data timings increases, leading to performance degradation over time due to factors like temperature and voltage changes, necessitating frequent retraining operations.
Innovation Solution
A memory system with a memory controller that performs real-time training operations based on error location information for data signals from memory devices during read operations, adjusting time codes to optimize data input/output timing without performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating speed of semiconductor devices is increased, then the data transmission rate is improved, but the skew of timings between clock, data strobe signal, and data increases
Solution Approach 1:
The patent implements dynamic adjustment of delay values through continuous training operations. The memory controller monitors error location information during read operations and adjusts delay values in real-time to compensate for timing skew, transforming a static timing system into a dynamic one that adapts to changing conditions.
Solution Approach 2:
The patent establishes a feedback mechanism where error location information from read operations is fed back to the training control module. This feedback loop enables the system to detect timing skew and automatically adjust delay values to minimize the skew, creating a closed-loop control system.
2Manufacturing precision
If delay values are set to optimal values by initial training operation, then timing skew is minimized, but data input/output timing changes over time due to temperature and voltage variations
Solution Approach 1:
The patent implements continuous training operations during read operations to continuously adjust delay values. This continuous action ensures that timing optimization is maintained throughout device operation, compensating for drift caused by temperature and voltage changes without interrupting normal operations.
Solution Approach 2:
The system performs self-adjustment by automatically detecting timing skew through error location information and correcting its own delay values without external intervention. The memory controller autonomously monitors and adjusts timing parameters to maintain optimal performance.
3Reliability
If training operation is performed again to compensate for timing changes, then timing skew is corrected, but significant performance degradation occurs
Solution Approach 1:
The patent performs partial training operations during read operations rather than complete retraining. By adjusting only the necessary delay values based on error location information from ongoing operations, the system corrects timing issues with minimal disruption to system performance.
Solution Approach 2:
The patent performs preliminary adjustments of delay values during read operations based on error location information. This preliminary action prevents significant timing degradation before it occurs, maintaining optimal performance continuously rather than correcting issues after they develop.
Data Source
AI summary
A memory system includes a plurality of memory devices; and a memory controller configured to perform an initial training operation to set a plurality of time codes corresponding to the plurality of memory devices, respectively, receive a plurality of data signals read from the plurality of memory devices, as internal data signals, according to the plurality of time codes, respectively, and adjust the plurality of time codes based on the internal data signals and error pattern maps generated by collecting error location information for the internal data signals.