Memory Controller Dynamic Timing Adjustment
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Solution Overview
Problem
Conventional memory controllers apply constant timing parameters to DRAM devices, leading to a bottleneck phenomenon when multiple row access operations are performed, which deteriorates the operational performance of DRAM devices.
Innovation Solution
A memory controller that adjusts timing parameters based on the time elapsed after a refresh operation, using a scheduler to decide the processing order of requests and a timing control circuit to vary timing parameters according to the corresponding address, thereby reducing the bottleneck phenomenon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If constant timing parameters are applied to multiple row access operations, then the device complexity is reduced and ease of operation is improved, but a bottleneck phenomenon occurs and productivity deteriorates
Solution Approach 1:
The patent implements dynamic timing parameters that automatically adjust based on the refresh status of memory rows. The timing control circuit monitors whether a row has been refreshed and selects appropriate timing values (tRP, tRCD, tRC) from different parameter sets, transforming the static timing system into a dynamic one that adapts to real-time memory state, thereby resolving the bottleneck phenomenon while maintaining operational simplicity
Solution Approach 2:
The patent changes the timing parameters (tRP, tRCD, tRC) based on the refresh completion status of memory rows. When a row is freshly refreshed, different timing values are applied compared to when the row is not refreshed, allowing the system to optimize performance for different operational conditions without requiring complex manual configuration
2Productivity
If multiple row access operations are performed sequentially with constant timing parameters, then the ease of operation is maintained, but processing delays occur and productivity is reduced
Solution Approach 1:
The patent performs preliminary refresh operations on memory rows before they are accessed. The refresh control circuit proactively refreshes rows in advance, and the timing control circuit detects this preliminary refresh status to apply optimized timing parameters for subsequent access operations, thereby reducing processing delays without requiring manual intervention
Data Source
AI summary
A memory controller includes a scheduler that decides a processing order of a plurality of requests provided from an external device with reference to a timing parameter value for each of the requests; and a timing control circuit that adjusts the timing parameter value according to a corresponding address to access a memory device, the corresponding address being used to process a corresponding request of the plurality of requests.