Memory Controller Dynamic Timing Scheduling

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Solution Overview

Problem

Current memory management systems face challenges in optimizing memory access and scheduling, particularly in integrating advanced memory technologies into existing systems without incurring excessive costs and complexity, while ensuring efficient performance and resource utilization.

Innovation Solution

A computing system and method that utilize a global scheduler to dynamically adjust timing schemes for memory access requests based on capacity and priority criteria, employing rotating priority queues and phase detection to optimize memory access between different memory sets, such as DRAM and 3D XPoint memory, through the use of DDR and DDR-T interfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If dedicated interfaces and sockets are added to integrate new memory technologies, then memory access performance is improved, but system cost and complexity increase

Engineering Contradiction:
Improvememory access performanceVSAvoidsystem complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The memory controller is designed to handle multiple memory types (DDR3, DDR4, LPDDR4, HBM2, HBM3) through a unified interface and common control logic. The controller can dynamically adapt to different memory technologies without requiring separate dedicated interfaces for each type, thereby improving memory access performance while avoiding the complexity and cost of multiple dedicated interfaces.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple memory types are integrated into the same system, then system versatility and performance are improved, but scheduling complexity and resource management difficulty increase

Engineering Contradiction:
Improvememory system versatilityVSAvoidscheduling complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory system is segmented into multiple memory channels, each capable of handling different memory types. The controller divides memory access requests into channel-specific operations, allowing independent management and optimization of each memory type while maintaining overall system versatility. This segmentation reduces scheduling complexity by localizing management tasks to specific channels rather than requiring global coordination.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The memory controller implements dynamic scheduling that adapts to varying workload requirements and memory type characteristics in real-time. The controller can dynamically adjust timing parameters, bandwidth allocation, and access patterns based on the specific memory types being accessed and the current system state, thereby managing multiple memory types efficiently without excessive scheduling complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP3462327B1Systems, methods and apparatus for memory access and scheduling
Publication Date: 2024.01.17 INTEL CORP
  • EP3462327B1 patent drawingFigure 1
  • EP3462327B1 patent drawingFigure 2
  • EP3462327B1 patent drawingFigure 3

AI summary

A memory controller method and apparatus, which includes a modification of at least one of a first timing scheme or a second timing scheme based on information about one or more data requests to be included in at least one of a first queue scheduler or a second queue scheduler, the first timing scheme indicating when one or more requests in the first queue scheduler are to be issued to the first memory set via a first memory set interface and over a channel, the second timing scheme indicating when one or more requests in the second queue scheduler are to be issued to the second memory set via a second memory set interface and over the channel. Furthermore, an issuance of a request to at least one of the first memory set in accordance with the modified first timing scheme or the second memory set in accordance with the modified second timing scheme may be included.